參數(shù)資料
型號(hào)： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 133/155頁
文件大小： 4139K
代理商： 5962R0722402VYC
AT697F PRELIMINARY INFORMATION
79
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Registers
Description
Table 29. Register legend
Address = 0x01010101
Bit Number
31
30
29
28
27
26
25
24
23
...
9
8
7
6
5
4
3
2
1
0
field name
field
reserved
bit
access type
r=read access
w=write acces
r/w=read and write access
default value after reset
0
100
1
x = undefined or non affected by reset
Integer Unit
Registers
Table 30. Processor State Register- PSR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
impl[3:0]
ver[3:0]
n
z
v
c
reserved
ec
ef
pil[3:0]
s
ps
et
cwp[4:0]
r
r/w
r
r/w
0001
x
xxxxxx
0
x
xxxx
1
00000
Bit Number
Mnemonic
Description
31..28
impl[3:0]
Implementation or class of implementations of the architecture.
27..24
ver[3:0]
Identify one or more particular implementations or is a readable and writable state field whose properties are
implementation-dependent.
23
n
indicates whether the ALU result was negative for the last instruction modifying icc field.
1 = negative
0 = not negative.
22
z
indicates whether the ALU result was zero for the last instruction modifying icc field.
1 = zero
0 = not zero.
21
v
indicates whether the ALU result was within the range of (was representable in) 32-bit 2’s complement notation
for the last instruction that modified the icc field. 1 = overflow, 0 = no overflow.
20
c
indicates whether a 2’s complement carry out (or borrow) occurred for the last instruction that modified the icc
field. Carry is set on addition if there is a carry out of bit 31. Carry is set on subtraction if there is borrow into bit
31. 1 = carry, 0 = no carry.
13
ec
determines whether the implementation-dependent oprocessor is enabled. If disabled, a coprocessor
instruction will trap. 1 = enabled, 0 = disabled. If an
implementation does not support a coprocessor in ardware, PSR.EC should always read as 0 and writes to it
should be ignored.
12
ef
determines whether the FPU is enabled. If disabled, a floating-point instruction will trap. 1 = enabled, 0 =
disabled. If an implementation does not support a hardware FPU, PSR.EF should always read as 0 and writes
to it should be ignored.
11..8
pil[3:0]
identify the interrupt level above which the processor will accept an interrupt.
7
s
determines whether the processor is in supervisor or user mode. 1 = supervisor mode, 0 = user mode.
6
ps
contains the value of the S bit at the time of the most recent trap.
5
et
determines whether traps are enabled. A trap automatically resets ET to 0. When ET=0, an interrupt request is
ignored and an exception trap causes the IU to halt execution, which typically results in a reset trap that
resumes execution at address 0. 1 = traps enabled, 0 = traps disabled.
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參數(shù)描述
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5962R0724902VPC 制造商:Intersil Corporation 功能描述:
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