參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 149/155頁
文件大小： 4139K
代理商： 5962R0722402VYC
Table 55. Fail Address Register - FAILAR
Address = 0x8000000C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
fa[31:0]
r
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
31..0
fa[31:0]
Failing Address
This field contains the address of the access that triggered an error response. This register is updated each
time an error occurs on the internal bus.
Table 56. Fail Status Register - FAILSR
Address = 0x80000010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ee
ev
rw
hmaster[3:0]
hsize[2:0]
r/w
r/w r/w
r
xxxxxxxxxxxxxxx
0
Bit Number
Mnemonic
Description
9
ee
EDAC Correctable error
Set when a correctable EDAC error is detected.
8
ev
Error Valid.
Set when a new error occurred.
7
rw
Read/Write.
This bit is set if the failed access was a read cycle, otherwise it is cleared.
6..3
hmaster[3:0]
AHB master.
This field contains the HMASTER[3:0] of the failed access.
2..0
hsize[2:0]
Transfer Size.
This filed contains the HSIZE[2:0] of the failed transfer.
AT697F PRELIMINARY INFORMATION
93
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Note:
Any access triggering an error response on the AHB bus will be registered in two registers; AHB
failing address register and AHB status register.The failing address register will store the address
of the access while the AHB status register will store the access and error type.The registers are
updated when an error occur, and the EV (error valid) is not set. When the EV bit is set, interrupt 1
is generated to inform the processor about the error. After an error, the EV bit has to be reset by
software.
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