參數(shù)資料
型號: 5962R0722402VYC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝: QFP-256
文件頁數(shù): 37/155頁
文件大?。?/td> 4139K
代理商: 5962R0722402VYC
AT697F PRELIMINARY INFORMATION
131
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
AC Characteristics The AT697 processor implements a single event transient protection mechanism. The influence
of this protection is reflected by the timing figures presented in the following tables.
The following tables show the timing figures for the skew condition natural and maximum.
Natural Skew
Test Conditions
Natural Skew
Temperature range : -55°C to 125°C
Voltage range :
I/O: 3.3V +/- 0.30V
Core: 1.8V +/- 0.15V
Output load : 50pF
Voltage threshold Test condition : Vcc/2
Table 126. AC Characteristics - Natural Skew
Parameter
Min
(ns)
Max
(ns)
Comment
Reference edge
(‘+’ for rising edge)
t1
10
CLK Period with PLL disable
t1_p
40
50
CLK Period with PLL enable
t2
4.5
CLK Low and High pulse width - PLL disabled
t2_p
18
CLK Low and High pulse width - PLL enabled
t3
10
SDCLK Period
t4
3
7
SDCLK output delay - PLL disabled
CLK
t5
1.107
PLL setup time
t6
1*t3
Reset Pulse Width
t10
1.5
7
A[27:0] output delay
SDCLK +
t11
2
8
D[31:0] and CB[7:0] output delay
SDCLK +
t12
4
D[31:0] and CB[7:0] setup time
SDCLK +
t13
0
D[31:0] and CB[7:0] hold time during load/fetch
SDCLK +
t14
0
9
D[31:0] and CB[7:0] hold time during write (see note below)
SDCLK +
t15
2
7
OE*, READ and WRITE* output delay
SDCLK +
t16
2
5.5
ROMS*[1:0] output delay
SDCLK +
t17
2
6
RAMS*[4:0], RAMOE*[4:0] and RWE*[3:0] output delay
SDCLK +
t18
2
5.5
IOS* output delay
SDCLK +
t19
5
BRDY* setup time
SDCLK +
t20
0
BRDY* hold time
SDCLK +
t21
3
8
SDCAS* output delay
SDCLK +
t22
2
8.5
SDCS*[1:0], SDRAS*, SDWE* and SDDQM*[3:0] output delay
SDCLK +
t23
4
BEXC* setup time
SDCLK +
t24
0
BEXC* hold time
SDCLK +
t25
2.5
9
PIO[15:0] output delay
SDCLK +
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