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參數(shù)資料
| 型號(hào)： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁數(shù)： | 109/155頁 |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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AT697F PRELIMINARY INFORMATION
57
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Target Mode
Transfer
In the target mode, the PCI interface receives requests originated from remote PCI initiators
(masters). Target data transfer is executed in background without AT697 core intervention.
AT697 core can only intervenes is the configuration of the target.
In host bridge mode the target is configured by the AT697 core
In satellite mode the configuration is done by a remote device using the PCI command set
Target Programming
The target is configured through the following registers :
PCISC register
bits 0/1 for memory and I/O command response
bit 6 for check of data and address parity error
bit 7 for response to data and address parity error
base address registers
memory base address : MEMBAR1, MEMBAR2
I/O base address : IOBAR
PCITPA register to indicate the storage location
PCITSC FRTY bit to write data in memory
transaction Ordering
As specified in the PCI standard, delayed read functionality is implemented, obeying to the fol-
lowing rules:
The interface stores one delayed read at a time. When a read request was retried (because
local data not yet available), the interface remains locked for any other target read (targeting
different addresses). The initiator of the original read has to repeat its request to the same
address.
A retried (delayed) read can be interrupted by one or more PCI write accesses. The PCI
standard requires this write command to be processed first, to prevent a system lock-up.
Meanwhile, the interface will prefetch read-data into the TXMT FIFO. After the (interfering)
write, when the read request is repeated, and the requested data is available in the FIFO the
delayed transfer completes normally.
All target read accesses are generally prefetching, also reads with I/O command. Once a start
address is given, the interface prefetches up to 8 words into the TXMT FIFO. After the last
required data word was transferred to PCI, the PCI core automatically flushes the FIFO to dis-
card the unused prefetched data. The interface assumes the complete local address space to be
‘prefetchable’, defined here as the fact, that reading from an address does not alter the data.
This behaviour is to be considered if non-prefetchable devices (for example the UART’s) shall
be read
through the PCI target.
PCI Error
Reporting
According to the PCI standard, error and status bits are implemented in the PCI status regis-
ter.(PCISC). The PCI standard foresees a single parity check, by which bus-errors can be
detected, but not corrected. Errors which occur in the PCI interface or on the PCI bus are also
saved in status bits in the PCIITP register, and optionally, the PCI interrupt (IRQ14) is asserted.
Different events can be selected to assert the interrupt. By the interrupt enable register (PCIITE)
configuration you can select the interrupt events which will assert IRQ14. then an interrupt han-
dler can read the interrupting event in the status register (PCIITP).
Furthermore, interrupts can be forced for test purposes by writing to PCIITF.
In host-bridge configuration, this allows an error detection by polling. Certain events and errors
are also reported by the interface in the interrupt status register. For each bit of this register ,
interrupt generation can be programmed individualy. All PCI interrupt generated are then
reported to AT697 core through the PCI interrupt (IT14). The different interrupt causes are distin-
guished by the interrupt status registers settings.
Please refer to the register description chapter for more details on interrupt status register.
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