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參數(shù)資料
| 型號(hào)： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁(yè)數(shù)： | 139/155頁(yè) |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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84
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Trap Types
The ftt field can be read by the STFSR instruction. An LDFSR instruction does not affect ftt field.
Table 41.
TT
Name
Description
0
none
No trap.
1
IEEE_exception
An IEEE_754_exception floating-point trap type indicates that a floating-point exception occurred that conforms to
the ANSI/IEEE Standard 754-1985. The exception type is encoded in the cexc field.
2
Unfinished_FPop
An unfinished_FPop indicates that an implementation’s FPU was unable to generate correct results or exceptions
3
unimplemented_FPop
An unimplemented_FPop indicates that an implementation’s FPU decoded an FPop that it does not implement. In
this case, the cexc field is unchanged
4
sequence_error
A sequence_error indicates one of three abnormal error conditions in the FPU, all caused by erroneous supervisor
software:
- An attempt was made to execute a floating-point instruction when the FPU was not able to accept one. This type
of sequence_error arises from a logic error in supervisor software that has caused a previous floating-point trap to
be incompletely serviced (for example, the floating-point queue was not emptied after a previous floating-point
exception).
- An attempt was made to execute a STDFQ instruction when the floatingpoint deferred-trap queue (FQ) was
empty, that is, when FSR.qne = 0. (Note that generation of sequence_error is recommended, but not required in
this case)
5
hardware error
A hardware_error indicates that the FPU detected a catastrophic internal error, such as an illegal state or a parity
error on an f register access. If a hardware_error occurs during execution of user code, it may not be possible to
recover sufficient state to continue execution of the user application.
6
invalid register
An invalid_fp_register trap type indicates that one (or more) operands of an FPop are misaligned, that is, a double-
precision register number is not 0 mod 2, or a quadruple-precision register number is not 0 mod 4. It is
recommended that implementations generate an fp_exception trap with FSR.ftt = invalid_fp_register in this case,
but an implementation may choose not to generate a trap.
Trap Type Definition
27..23
tem[4:0]
Trap Enable Mask
tem field enables traps caused by FPops. These bits are ANDed with the bits of the cexc (current exception
field) to determine whether to force a floating-point exception to IU. All trap enable fields correspond to the
similarly named bit in the cexc field.
0 = trap disabled
1 = trap enabled
22
ns
Causes the FPU to produce implementation-defined results that may not correspond to ANSI/IEEE Standard
754-1985. For instance, to obtain higher performance, implementations may convert a subnormal floatingpoint
operand or result to zero when NS is set.
19..17
ver[2:0]
Identify one or more particular implementations of the FPU architecture. For each SPARC IU implementation
there may be one or more FPU implementations, or none. This field identifies the particular FPU implementation
present.
16..14
ftt[2:0]
Floating point trap type
Identify floating-point exception trap types.when floating point exception occurs, the ftt field encodes the type of
floating-point exception until an STFSR or another FPop is executed.
11..10
fcc[1:0]
Contain the FPU condition codes. These bits are updated by floating-point compare instructions (FCMP and
FCMPE). They are read and written by the STFSR and LDFSR instructions, respectively. FBfcc bases its
control transfer on this field.
9..5
aexc[4:0]
Accumulate IEEE floating-point exceptions while fp_exception traps are disabled using the TEM field. After an
FPop completes, the TEM and cexc fields are logically anded together. If the result is nonzero, an fp_exception
trap is generated; otherwise, the new cexc field is or’d into the aexc field. Thus, while traps are masked,
exceptions are accumulated in the aexc field.
4..0
cexc[4:0]
Indicate that one or more IEEE floating-point exceptions were generated by the most recently executed FPop
instruction. The absence of an exception causes the corresponding bit to be cleared.
Bit Number
Mnemonic
Description
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