參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 86/155頁
文件大小： 4139K
代理商： 5962R0722402VYC
36
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
during a PROM read access. Setting MCFG1
PRWWS defines the number of waitstates to
insert during a PROM write.
MCFG1 PRRWS and MCFG1 PRWWS can be programmed to take values from 0 up to 15.
The effective number of waitstates applied during an access is then twice the programmed
value. In that way, programming two waitstates results in the insertion of four wait cycles during
the access.
Figure 20. ROM read access with PRRWS=1 (two programmed waitstate
data2
waitstate
D1
lead-out
A1
CLK
A
ROMS*
D
OE*
data1
waitstate
s)
If the application needs more time for ROM transfer, it is possible to introduce more delay by
activating the hardware bus ready MCFG1 PBRDY. Refer to paragraph “BRDY Wait states”,
After a reset operation of the processor (or at power up), the MCFG1
PRRWS and
MCFG1 PRWWS waitstates for the PROM area are set default to 15, resulting in 30 effective
waitstates and the MCFG1 PBRDY is set to 0.
Write Protection
Write protection is provided to prevent accidental over-writing to PROM area. It is controlled
through the PROM write enable bit MCFG1
PRWE. When set 1, this bit enables write to
PROM. When set 0, no PROM write transaction is available.
Bus width
To support applications with low memory and performance requirements, the PROM area can
be configured for 8-bit operations. The configuration of PROM in 8-bit mode is done program-
ming MCFG1 PRWDH.
When the PROM bus is configured as an 8-bit wide bus, data 31 downto 24 shall be used as
interface.
Figure 21.
CS
OE
WE
A
D
PROM
OE*
AD
AT697F
A[27:0]
D[31:24]
A[27:0]
WRITE*
ROMS0*
PROM 8-bit bus width connection
Since access to memory is always done on 32-bit word basis, read access to 8-bit memory will
be transformed in a burst of four read transactions. If EDAC protection is active, 5 read cycles
are necessary to complete the access (please refer to protection section for more details). Dur-
ing write operation, only the necessary bytes are writen.
Access Error
An access error can be indicated to the processor asserting the BEXC* signal. If enabled by set-
ting logical one to MCFG1 BEXC , the BEXC* signal is sampled with the data.
Trap 0x01 is taken if an instruction fetch is in progress
Trap 0x09 is taken if a data space is in progress
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