參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 87/155頁
文件大小： 4139K
代理商： 5962R0722402VYC
AT697F PRELIMINARY INFORMATION
37
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Trap 0x2B is taken if a data store is in progress
Memory Mapped
I/O
Overview
The memory controller give the capability to control up to 256Mbyte of I/O. The I/O area consists
in a single large bank. The control of the I/O area accesses uses a standard set of pin, including
chip selects (IOS*x), output enable (OE*), read (READ) and write (WRITE*) lines.
The size of the I/O bank is not programmable. The entire I/O area (0x20000000 up to
0x2FFFFFFF) is controlled by the IOS* select signal.
I/O Read Access
A read access to I/O consists in a lead-in cycle, two data cycles, waitstates if any programmed
and a lead-out cycle. On non-consecutive accesses, the lead-out cycle is used to prevent bus
contention due to slow turn-off time of memories or I/O devices.
The I/O select signal (IOSEL*) is delayed one clock to provide stable address.
Figure 22. single I/O read transaction with lead-out
lead-in
data 2
D1
lead-out
A1
CLK
A
IOS*
D
OE*
data 1
I/O Write Access
Each write access to I/O consists of three states and of waitstates if any programmed. The three
mandatory states are divided in one write setup cycle, one data cycle and one lead-out cycle.
The write operation is strobed by the WRITE* signal.
Figure 23. I/O write transaction
lead-in
data
lead-out
D1
A1
CLK
A
IOS*
D
WRITE*
Waitstates
For application using slow I/O devices, the I/O controller provides the capability to insert wait-
states during the accesses. Two types of wait-states can be inserted :
Programmed delay,
‘Hardware’ delay.
Up to 15 waitstates can be programmed for I/O accesses. Read and write waitstates are pro-
grammed simultaneously. Setting MCFG1
IOWS defines the number of waitstates to insert
during any access to/from I/O areas. MCFG1 IOWS can be programmed to take values from 0
up to 15.
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