參數(shù)資料
型號(hào): 5962R0722402VYC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝: QFP-256
文件頁數(shù): 2/155頁
文件大?。?/td> 4139K
代理商: 5962R0722402VYC
10
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Pin Description
ATMEL Convention
‘*’ attached to a signal (e.g OE*) designate an active-low signal.
When a bit of a register is writen in C-like style (e.g MCFG2 RAMWWS) it must be read as the
RAMWWS bit in the register MCFG2.
IU and FPU Signals
A[27:0] - Address bus (output)
A[27:0] bus carries the addresses during accesses to external memory. When access to cache
memory is performed, the address of the last external memory access remains driven on the
address bus.
D[31:0] - Data bus (bi-directional)
D[31:0] bus carries the data during accesses to memory. The processor automatically config-
ures the bus as output and drive the lines during write transactions.
During accesses to 8-bit areas, only D[31:24] are used.
CB[7:0] - Check bits (bi-directional)
CB[6:0] bus carries the EDAC checkbits during memory accesses. CB[7]
(1) takes the value of
tcb[7] in the error control register. Processor only drives CB[7:0] during write transactions to
areas programmed to be EDAC protected.
Note:
1. CB[7] is implemented to enable programming of flash memories. When only 7 bits are useful
for EDAC protection, 8 are needed for programming.
Memory Interface
Signals
General management
OE* - Output enable (output)
This active low output is asserted during read transactions on the memory bus.
BRDY* - Bus ready (input)
When driven low, this input indicates to the processor that the current memory access can be
terminated on the next rising clock edge. When driven high, this input indicates to the processor
that it must wait and not end the current access.
READ - Read transaction (output)
This active high output is asserted during read transactions on the memory bus.
WRITE* - Write enable (output)
This active low output provides a write strobe during write transactions on the memory bus.
PROM
ROMS*[1:0] - PROM chip-select (output)
These active low outputs provide the chip-select signal for the PROM area. ROMS*[0] is
asserted when the lower half of the PROM area is accessed (0 - 0x10000000), while ROMS*[1]
is asserted for the upper half.
SRAM
RAMOE*[4:0] - RAM output enable (output)
These active low signals provide an individual output enable for each RAM bank.
RAMS*[4:0] - RAM chip-select (output)
These active low outputs provide the chip-select signals for each RAM bank.
RWE* [3:0] - RAM write enable (output)
These active low outputs provide individual write strobes for each byte. RWEN[0] controls
D[31:24], RWEN[1] controls D[23:16], etc.
I/O
IOS* - I/O select (output)
相關(guān)PDF資料
PDF描述
5962R8958702VXA 5 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, CDSO16
5962R9215311VTA 32K X 8 STANDARD SRAM, 55 ns, CDFP36
5962R9215311VTX 32K X 8 STANDARD SRAM, 55 ns, CDFP36
5962G9215309VMX 32K X 8 STANDARD SRAM, 55 ns, CDIP28
5962F9215315VMC 32K X 8 STANDARD SRAM, 70 ns, CDIP28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962R0722601VZA 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays
5962R0722701VZA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
5962R0722902VXA 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓(最大值):307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
5962R0722961VXA 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓(最大值):307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
5962R0724902VPC 制造商:Intersil Corporation 功能描述: