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參數(shù)資料
| 型號(hào)： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁(yè)數(shù)： | 66/155頁(yè) |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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18
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
A correction counter asr16 cnt is provided for error management. The asr16 cnt field is incre-
mented each time a register correction is performed. It saturates at “111”.
State Register
The State Register (PSR) contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional opera-
tions. Note that the Status Register is updated after all ALU operations, as specified in the SPARC
architecture specification. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The state also provides some global information on the current window used, the authorized
interrupts and peripheral (FPU and coprocessor) presence. A global interrupt management is
provided through the processor state register. Trap and Interrupts can be individually
enabled/disables from within this register.
Instruction Set
AT697F instructions fall into six functional categories: load/store, arithmetic/logical/ shift, control
transfer, read/write control register, floating-point, and miscellaneous. Please refer to SPARC V8
Architecture manual that presents all the implemented instructions.
Floating Point Unit The FPU is designed to provide execution of single and double-precision floating-point instruc-
tions. During the execution of floating-point instructions the processor pipeline is held.
The FPU is designed for highly dependable space and military applications, by including fault
tolerance features like error detection and correction and triple modular redundancy.
The FPU depends upon the IU to access all addresses and control signals for memory access.
Floating-point loads and stores are executed in conjunction with the IU, which provides
addresses and control signals while the FPU supplies or stores the data. Instruction fetch for
integer and floating-point instructions is provided by the IU.
The FPU contains 32 32-bit floating-point f registers, which are numbered from f[0] to f[31].
Unlike the windowed r registers, at a given time an instruction has access to any of the 32 f reg-
isters. The f registers can be read and written by FPop (FPop1/FPop2 format) instructions, and
by load/store single/double floating-point instructions (LDF, LDDF, STF, STDF).
Rounding Direction
Rounding direction for floating point results is built according to the ANSI/IEEE Standard 754-
1985.
In this way,
0 = round to nearest
1 = round to zero
2 = round to +infinity
3 = round to -infinity
Figure 4. Rounding Direction Schematic
0
Value > 0
Value < 0
round to
-
∞
-
∞
+
∞
round to
-
∞
round to
+
∞
round to
+
∞
round to zero
Fault Tolerance
The processor has been especially designed for space application. To prevent erroneous opera-
tions from single event transient (SET) and single event upset (SEU) errors, the AT697F
processor implements a set of protection features including :
Full triple modular redundancy (TMR) architecture
The TMR architecture is based on a fully triplicated clock distribution (CLK1, CLK2 and
CLK3). The PCI clock and the CPU clock are built as three-clock trees. The same triplication
is applied to the PCI reset and to the CPU reset. See figure 5 for an overview of the TMR
architecture.
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| 5962R0722601VZA | 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays |
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