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參數(shù)資料
| 型號(hào)： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁(yè)數(shù)： | 15/155頁(yè) |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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AT697F PRELIMINARY INFORMATION
111
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
24
stat8
Master received/asserted PERR
This bit is only implemented by bus masters. It is set when three conditions are met:
1) the bus agent asserted PERR* itself (on a read) or observed PERR* asserted (on a write);
2) the agent setting the bit acted as the bus master for the operation in which the error occurred;
3) the Parity Error Response bit (Command register) is set.
23
stat7
Target supports fast back2back
This optional read-only bit indicates whether or not the target is capable of accepting fast back-to-back
transactions when the transactions are not to the same agent. This bit can be set to 1 if the device can accept
these transactions and must be set to 0 otherwise.
22
stat6
User definable features
21
stat5
66 MHz capabality
This optional read-only bit indicates whether or not this device is capable of running at 66 MHz as defined in
Chapter 7. A value of zero indicates 33 MHz. A value of 1 indicates that the device is 66 MHz capable
20
stat4
Power management capability.
This optional read-only bit indicates whether or not this device implements the pointer for a New Capabilities
linked list at offset 34h. A value of zero indicates that no New Capabilities linked list is available. A value of one
indicates that the value read at offset 34h is a pointer in Configuration Space to a linked list of new capabilities.
10
com10
Interrupt command.
This bit disables the device/function from asserting INTx*. A value of 0 enables the assertion of its INTx*
signal. A value of 1 disables the assertion of its INTx* signal. This bit’s state after RST* is 0.
9
com9
Master can generate fast back2back.
This optional read/write bit controls whether or not a master can do fast back-to-back transactions to different
devices. Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the
master is allowed to generate fast back-to-back transactions to different agents. A value of 0 means fast back-
to-back transactions are only allowed to the same agent. This bit's state after RST* is 0.
8
com8
Enable SERR driver
-This bit is an enable bit for the SERR* driver. A value of 0 disables the SERR* driver. A value of 1 enables
the SERR* driver. This bit's state after RST* is 0. All devices that have an SERR* pin must implement this bit.
Address parity errors are reported only if this bit and bit 6 are 1.
7
com7
Address/Data stepping on PCI bus
6
com6
Enable Parity Check
This bit controls the device's response to parity errors. When the bitis set, the device must take its normal
action when a parity error is detected. When the bit is 0, the device sets its Detected Parity Error status bit (bit
15 in the Status register) when an error is detected, but does not assert PERR* and continues normal
operation. This bit's state after RST* is 0. Devices that check parity must implement this bit. Devices are still
required to generate parity even if parity checking is disabled.
5
com5
VGA palette snooping
This bit controls how VGA compatible and graphics devices handle accesses to VGA palette registers. When
this bit is 1, palette snooping is enabled (i.e., the device does not respond to palette register writes and snoops
the data). When the bit is 0, the device should treat palette write accesses like all other accesses. VGA
compatible devices should implement this bit.
4
com4
Enable memory write and invalidate. This is an enable bit for using the Memory Write and Invalidate command.
When this bit is 1, masters may generate the command. When it is 0, Memory Write must be used instead.
State after RST* is 0. This bit must be implemented by master devices that can generate the Memory Write and
Invalidate command.
3
com3
Enable special cycles
Controls a device's action on Special Cycle operations. A value of 0 causes the device to ignore all Special
Cycle operations. A value of 1 allows the device to monitor Special Cycle operations. State after RST* is 0.
2
com2
Enable PCI master
Controls a device's ability to act as a master on the PCI bus. A value of 0 disables the device from generating
PCI accesses. A value of 1 allows the device to behave as a bus master. State after RST* is 0.
1
com1
Enable target memory command response
Controls a device's response to Memory Space accesses. A value of 0 disables the device response. A value of
1 allows the device to respond to Memory Space accesses. State after RST* is 0.
Bit Number
Mnemonic
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962R8958702VXA | 5 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, CDSO16 |
| 5962R9215311VTA | 32K X 8 STANDARD SRAM, 55 ns, CDFP36 |
| 5962R9215311VTX | 32K X 8 STANDARD SRAM, 55 ns, CDFP36 |
| 5962G9215309VMX | 32K X 8 STANDARD SRAM, 55 ns, CDIP28 |
| 5962F9215315VMC | 32K X 8 STANDARD SRAM, 70 ns, CDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962R0722601VZA | 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays |
| 5962R0722701VZA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| 5962R0722902VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| 5962R0722961VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類(lèi)型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| 5962R0724902VPC | 制造商:Intersil Corporation 功能描述: |
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