- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45222 > MC68HC05PD6 (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 95/165頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MC68HC05PD6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁當前第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
INTERRUPTS
MOTOROLA
REV 1.1
4-1
SECTION 4
INTERRUPTS
The MCU can be interrupted in seven different ways:
Non-maskable Software Interrupt Instruction (SWI)
P-Decoder Interrupt
External Interrupt (IRQ)
Key Wake-Up Interrupt (KWI)
Timer Interrupt
SCI Interrupt
RTC Interrupt
4.1
CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set the
interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts
do not cause the current instruction execution to be halted, but are considered pending
until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is cleared) and the corresponding interrupt
enable bit is set the processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs the processor completes the
current instruction, then stacks the current CPU register states, sets the I-bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If more than one
interrupt is pending following the stacking operation, the interrupt with the highest vector
location shown in Table 4-1 will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the appropriate
interrupt software service routine from the vector table at locations $FFF0 thru $FFFF as
defined in Table 4-1.
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from the
stack and normal processing to resume at the next instruction that was to be executed
when the interrupt took place. Figure 4-1 shows the sequence of events that occur during
interrupt processing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC705PD6 | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| MC68HC05PE0P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05PE0CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05PL4CSD | 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705PL4BDW | 8-BIT, OTPROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05PV8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05PV8A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05RC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16FN | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
發(fā)布緊急采購，3分鐘左右您將得到回復。