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參數(shù)資料
| 型號(hào)： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁(yè)數(shù)： | 95/165頁(yè) |
| 文件大小： | 841K |
| 代理商： | MC68HC05PD6 |
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July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
INTERRUPTS
MOTOROLA
REV 1.1
4-1
SECTION 4
INTERRUPTS
The MCU can be interrupted in seven different ways:
Non-maskable Software Interrupt Instruction (SWI)
P-Decoder Interrupt
External Interrupt (IRQ)
Key Wake-Up Interrupt (KWI)
Timer Interrupt
SCI Interrupt
RTC Interrupt
4.1
CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set the
interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts
do not cause the current instruction execution to be halted, but are considered pending
until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is cleared) and the corresponding interrupt
enable bit is set the processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs the processor completes the
current instruction, then stacks the current CPU register states, sets the I-bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If more than one
interrupt is pending following the stacking operation, the interrupt with the highest vector
location shown in Table 4-1 will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the appropriate
interrupt software service routine from the vector table at locations $FFF0 thru $FFFF as
defined in Table 4-1.
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from the
stack and normal processing to resume at the next instruction that was to be executed
when the interrupt took place. Figure 4-1 shows the sequence of events that occur during
interrupt processing.
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