參數(shù)資料
型號(hào): MC68HC05PD6
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 163/165頁
文件大?。?/td> 841K
代理商: MC68HC05PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
LCD DRIVER
MOTOROLA
REV 1.1
10-1
SECTION 10
LCD DRIVER
The LCD driver may be congured with 4 Backplanes (BP) and 36 Frontplanes
(FP) maximum. The VDD voltage is the highest level of the output waveform and
the lower three levels are VLCD1, VLCD2, and VLCD3. VLCD3 can be externally
driven, while VLCD1 and VLCD2 are internally generated.
On reset, LCD enable bit (LCDE) in the LCD control register (LCDCR) is cleared
(LCD drivers at a disabled state) and all BP and FP pins output Vdd level.
The LCD clock is generated by the Time Base module and LCLK bit in the TBCR1
selects clock frequency.
10.1
LCD WAVEFORM EXAMPLES
The following gures illustrate the LCD timing examples.
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