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| 型號(hào)： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁(yè)數(shù)： | 14/165頁(yè) |
| 文件大?。?/td> | 841K |
| 代理商： | MC68HC05PD6 |
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GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC05PD6
11-8
REV 1.1
11.9.3 Serial Communications Control Register 2 (SCCR2)
The serial communications control register 2 (SCCR2) provides the control bits
which: individually enable/disable the transmitter or receiver, enable the system
interrupts, and provide the wake-up enable bit and a “send break code” bit. Each
of these bits is described below. (The individual ags are discussed in the
TIE
When the transmit interrupt enable bit is set, the SCI interrupt occurs provided
TDRE is set (see Figure 11-1). When TIE is cleared, the TDRE interrupt is
disabled. Reset clears the TIE bit.
TCIE
When the transmission complete interrupt enable bit is set, the SCI interrupt
occurs provided TC is set (see Figure 11-1). When TCIE is clear, the TC
interrupt is disabled. Reset clears the TCIE bit.
RIE
When the receive interrupt enable bit is set, the SCI interrupt occurs provided
OR is set or RDRF is set (see Figure 11-1). When RIE is cleared, the OR and
RDRF interrupts are disabled. Reset clears the RIE bit.
ILIE
When the idle line interrupt enable bit is set, the SCI interrupt occurs provided
IDLE is set (see Figure 11-1). When ILIE is cleared, the IDLE interrupt is
disabled. Reset clears the ILIE bit.
WAKE
M
METHOD OF RECEIVER ‘WAKEUP’
0X
Detection of an idle line allows the next data byte received to cause
the receive data register to fill and produce an RDRF.
10
Detection of a received one in the eight data bit allows an RDRF flag
and associated error flags.
11
Detection of a received one in the ninth data bit allows an RDRF flag
and associated error flag.
0
7
0000000
6543210
W
R
SCCR2
$000C
reset
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
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