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參數(shù)資料
| 型號： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 15/165頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MC68HC05PD6 |
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July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
REV 1.1
11-9
TE
When the transmit enable bit is set, the transmit shift register output is applied
to the TDO line. Depending on the state of control bit M in serial
communications control register 1, a preamble of 10 (M=0) or 11 (M=1)
consecutive ones is transmitted when software sets the TE bit from a cleared
state. If a transmission is in progress, and TE is written to a zero, then the
transmitter will wait until after the present byte has been transmitted before
placing the TDO pin in the idle high-impedance state. If the TE bit has been
written to a zero and then set to a one before the current byte is transmitted, the
transmitter will wait until that byte is transmitted and will then initiate
transmission of a new preamble. After the preamble is transmitted, and
provided the TDRE bit is set (no new data to transmit), the line remains idle
(driven high while TE = 1); otherwise, normal transmission occurs. This function
allows the user to “neatly” terminate a transmission sequence. After loading the
last byte in the serial communications data register and receiving the interrupt
from TDRE, indicating the data has been transferred into the shift register, the
user should clear TE. The last byte will then be transmitted and the line will go
idle (high impedance). Reset clears the TE bit.
RE
When the receive enable bit is set, the receiver is enabled. When RE is
cleared, the receiver is disabled and all of the status bits associated with the
receiver (RDRF, IDLE, OR, NF, and FE) are inhibited. Reset clears the RE bit.
RWU
When the receiver wake-up bit is set, it enables the “wake up” function. The
type of “wake up” mode for the receiver is determined by the WAKE bit
discussed above (in the SCCR1). When the RWU bit is set, no status ags will
be set. Flags which were set previously will not be cleared with RWU is set. If
the WAKE bit is cleared, RWU is cleared after receiving 10 (M=0) or 11 (M=1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle.
If the WAKE bit is set, RWU is cleared after receiving an address bit. The RDRF
ag will then be set and the address byte will be stored in the receiver data
register. Reset clears the RWU bit.
SBK
When the send break bit is set the transmitter sends zeros in some number
equal to a multiple of the data format bits. If the SBK bit is toggled set and clear,
the transmitter sends 10 (M=0) or 11 (M=1) zeros and then reverts to idle or
sending data. The actual number of zeros sent when SBK is toggled depends
on the data format set by the M bit in the serial communications control register
1; therefore, the break code will be synchronous with respect to the data
stream. At the completion of the break code, the transmitter sends at least one
high bit to guarantee recognition of a valid start bit. Reset clears the SBK bit.
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