參數(shù)資料
型號: MC68HC05PD6
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 128/165頁
文件大?。?/td> 841K
代理商: MC68HC05PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
CLOCK DISTRIBUTION
MOTOROLA
REV 1.1
8-5
Figure 8-2. Time Base Clock Divider
8.4.1 LCDCLK
The clocks divided by 64 and 128 are used as LCD clock at the LCD driver
module, and clocks are selected by the LCLK bit in the TBCR1.
8.4.2 STUP
Time Base divider is initialized to $0078 by the power on detection and when the
count reaches 8072, STUP ag in the MISC register is set. Once STUP ag is set,
it is never cleared until power down.
8.4.3 Watchdog Timer (COP)
The Computer Operating Properly Watchdog Timer (COP) is controlled by the
COPE bit in the TBCR2 register.
S
E
L
7 BIT
DIVIDER
S
E
L
S
E
L
DIVIDE BY 4
TBCLK
LCLK
7 BIT
DIVIDER
RTR1
RTR0
COP
ENABLE
COP
CLEAR
COP
RESET
LCD
CLOCK
1/26
1/27
1/20
1/25
1/26
1/27
XCLK
OSC/27
0
1
0
1
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