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| 型號： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 31/165頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MC68HC05PD6 |
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GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
P-DECODER
MC68HC05PD6
12-10
REV 1.1
12.4
REGISTERS
There are several registers associated with the P-Decoder as described below.
12.4.1 P-Decoder Control Register 1 (PDCR1)
PDEN – P-Decoder Enable
If the PDEN bit is set, the P-Decoder module is enabled, If PDEN is cleared,
the module is reset and disabled.
PROGC – Programming Completed
If the PROGC bit is set, the P-Decoder system is enabled. This bit must be
CLEARed before the 6 user addresses and bits in PDCR2 and PDCR3 have
been set. Once PROGC is set, user cannot change the data contents in
PDCR2, PDCR3 and the 6 user address registers.
DCIE – Data Received Complete Interrupt Enable
When the DCIE is set, interrupt occurs when all the data is received completely
provided the DCF in the status register is set and the I-bit in the Condition Code
Register is cleared. If DCIE is cleared, this interrupt is disabled.
DBIE – Data Receiving Begin Interrupt Enable
When the DBIE is set, interrupt occurs when it begins to receive data into the
address and message registers provided the DBF in the status register is set
and the I-bit in the Condition Code Register is cleared. If DBIE is cleared, this
interrupt is disabled.
MSGIE – Message Received Interrupt Enable
When the MSGIE is set, interrupt occurs when 20 bits of message has been
stored in the Received Message Information Registers provided the MSGF in
the status register is set and the I-bit in the Condition Code Register is cleared.
If MSGIE is cleared, this interrupt is disabled.
ADRIE – Address Received Interrupt Enable
When the ADRIE is set, interrupt occurs when 3 bits of address and 2 function
bits has been stored in the Received Address Information Register provided
the ADRF in the status register is set and the I-bit in the Condition Code
Register is cleared. If ADRIE is cleared, this interrupt is disabled.
W
R
PDCR1
$0011
reset
PDEN
0
7
00
54
0
0000
6
3210
0
DCIE
DBIE
MSGIE
ADRIE
0
PROGC
option
map
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