參數(shù)資料
型號(hào)： MC68HC05PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 28/165頁
文件大小： 841K
代理商： MC68HC05PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
P-DECODER
MOTOROLA
REV 1.1
12-7
12.3.5 Mode Generator
There are four kinds of operating modes in the P-Decoder as shown in
Figure 12-4: programming, waiting, preamble and receiving mode.
Figure 12-4. Mode Transition Diagram
12.3.6 Programming Mode
The P-Decoder is in programming mode when the PROGC bit in the PDCR1 is
not set. PDCR1, PDCR2 and the six user address registers should be dened
before the PROGC bit is set. After PROGC is set, the P-Decoder enter the waiting
mode and the contents of PDCR1, PDCR2 and the six user address registers can
no longer be modied until PROGC bit is cleared again.
12.3.7 Waiting Mode
The operating mode changes to waiting mode from preamble mode after the
PROGC bit is set. In the waiting mode, the three battery saving signals toggle
periodically. Figure 12-5 shows the timing relationship. When BS1 = 1 and BS2 =
0, the P-Decoder synchronizes the incoming data from RF circuit to the rising
edge of bit clock and checks 6 bits of the preamble pattern. If there is a preamble
pattern, it will enter the preamble mode. Otherwise, it will stay in the waiting mode.
After the operating mode changes from the receiving mode to the waiting mode,
the P-Decoder will synchronize to the position of the Synchronization Code (SC).
Within tb1o interval, it receives 32 bits of data to check whether it is the SC. If it is
the SC, it will enter the receiving mode again. Otherwise, it will stay in the waiting
mode.
Programming
Waiting
Preamble
Receiving
sc_det=0
PROGC=1
sc_det=0
sc_det=1
pr_det=1
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