參數(shù)資料
型號(hào): MC68HC05PD6
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 32/165頁
文件大?。?/td> 841K
代理商: MC68HC05PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
P-DECODER
MOTOROLA
REV 1.1
12-11
12.4.2 P-Decoder Control Register 2 (PDCR2)
FB specify the frame number that the 6 user dened addresses belong to.
12.4.3 P-decoder Control Register 3 (PDCR3)
PLL1, PLL0
These 2 bits decide the time that BS3 goes high before BS1. When the data
speed is congured to 512 bps or 1200 bps, BS3 timing looks like the table
shown in Table 12-1. When the data speed is congured to 2400 bps, BS3
timing is shown in the following table.
Table 12-2. Frame Number Denition
FA / FB
Frame number
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
W
R
PDCR2
$0012
reset
0
7
00
54
0
0000
6
3210
FB2
0
FB1
FB0
option
map
W
R
PDCR3
$0013
reset
PLL1
0
7
00
54
0
0000
6
3210
PLL0
DPOL
FA2
FA1
FA0
DS1
DS0
option
map
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