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參數(shù)資料
| 型號： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 114/165頁 |
| 文件大小： | 841K |
| 代理商： | MC68HC05PD6 |
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GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05PD6
7-2
REV 1.1
corresponding KWIE
x bit in the KWIEN should be disabled, otherwise KWI
interrupt will occur.
When a Port B pin is programmed as an output by the corresponding DDRB bit,
data in the PORTB data register becomes output data to the pin and this data is
returned when PORTB register is read.
Pull-up resistors are provided for both upper and lower 4 bits of Port B pins which
are controlled by the RBH and RBL bits, respectively, in the RCR1 register. (The
typical resistor values are 200K
at V
DD=3V.)
7.3
PORT C
Port C pins share functions with several on chip peripherals. A pin function is
controlled by the enable bit of each associated peripheral.
Bit 7 and bit 6 of Port C are general purpose I/O pins and IRQ input pins. The
DDRC7/6 bits determine whether the pin states or the data latch states should be
read by the CPU. Since IRQ1(2)F can be set by either the pins or the data latches,
when using IRQs, be sure to clear the ags by software before enabling the
IRQ1(2)E bits.
The PC5 pin is a general purpose I/O pin and the direction of the pin is
determined by the DDRC5 bit in the Data Direction Register C (DDRC). When the
event output (EVO) is enabled, the PC5 is congured as an event output pin and
the DDRC5 bit has meaning only for the read of PC5 bit in the PORTC register; if
the DDRC5 is set the PC5 data latch is read by the CPU, otherwise PC5 pin level
(EVO state) is read. When EVO is disabled, it becomes general purpose I/O pin,
PC5. This PC5/EVO output has the capability to drive 10 mA source current when
(VOH ≥ Vdd–0.8V).
The PC4 and PC3 pins share functions with the Timer input pins (EVI and TCAP).
These bits are not affected by the usage of timer input functions and the directions
of pins are always controlled by the DDRC4 and DDRC3 bits. Also the DDRC4
and DDRC3 bits determine whether the pin states or data latch states should be
read by the CPU.
NOTE
Since the TCAP pin is shared with the PC3 I/O pin, changing the
state of the PC3 DDR or Data Register can cause an unwanted
TCAP interrupt. This can be handled by clearing the ICIE bit before
changing the conguration of PC3, and clearing any pending
interrupts before enabling ICIE.
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