參數(shù)資料
型號(hào)： MC68HC05PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 138/165頁
文件大?。?/td> 841K
代理商： MC68HC05PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
TIMER SYSTEM
MC68HC05PD6
9-2
REV 1.1
Because the timer has a 16-bit architecture, each specic functional segment
(capability) is represented by two registers. These registers contain the high and
low byte of that functional segment. Generally, accessing the low byte of a specic
timer function allows full control of that function; however, an access of the high
byte inhibits that specic timer function until the low byte is also accessed.
NOTE
The I bit in the CCR should be set while manipulating both the high
and low byte register of a specic timer function to ensure that an
interrupt does not occur.
9.1.1 Counter
The key element in the programmable timer is a 16-bit, free-running counter or
counter register, preceded by a prescaler that divides the internal processor clock
by four. The prescaler gives the timer a resolution of 2 microseconds if the internal
bus clock is 2.0 MHz. The counter is incremented during the low portion of the
internal bus clock. Software can read the counter at any time without affecting its
value.
The double-byte, free-running counter can be read from either of two locations,
$18-$19 (counter register) or $1A-$1B (counter alternate register). A read from
only the least signicant byte (LSB) of the free-running counter ($19, $1B)
receives the count value at the time of the read. If a read of the free-running
counter or counter alternate register rst addresses the most signicant byte
(MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value
remains xed after the rst MSB read, even if the user reads the MSB several
times. This buffer is accessed when reading the free-running counter or counter
alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter alternate
register, if the MSB is read, the LSB must also be read to complete the sequence.
The counter alternate register differs from the counter register in one respect: a
read of the counter register LSB can clear the timer overow ag (TOF).
Therefore, the counter alternate register can be read at any time without the
possibility of missing timer overow interrupts due to clearing of the TOF.
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