參數(shù)資料
型號(hào)： MC68HC05PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 115/165頁
文件大?。?/td> 841K
代理商： MC68HC05PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
INPUT/OUTPUT PORTS
MOTOROLA
REV 1.1
7-3
NOTE
Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should
always be cleared whenever EVI is used. EVI should not be used
when DDRC4 is high.
The PC2 pin is a general purpose I/O pin and the direction of the pin is
determined by the DDRC2 bit in the Data Direction Register C (DDRC). When the
Output Compare (TCMP) is enabled, the PC2 is congured as TCMP output pin
and the DDRC2 bit has meaning only for the read of PC2 bit in the PORTC
register; if the DDRC2 is set the PC2 data latch is read by the CPU, otherwise
PC2 pin level is read. When TCMP is disabled, it becomes general purpose I/O
pin, PC2. This PC2/TCMP output has the capability to drive 10 mA source current
when (VOH ≥ Vdd–0.8V).
The PC1 thru PC0 pins are shared with the Serial Communication Interface (SCI).
When the SCI is not used (TE, RE = 0), DDRC1 and DDRC0 bits control the
directions of the pins, and when the SCI is enabled, the pins are congured as
transmit data out (TDO) and receive data in (RDI). When the PORTC is read, the
value read will be determined by the Data Direction Register. When the port is
congured for input (DDRC1 or DDRC0 equal to 0) the pin state is read. When the
port is congured for output (DDRC1 or DDRC0 equal to 0) output data latch is
read.
Each Port C pin has pull-up resistor option which is controlled by the
corresponding RCR2 register bit. (The typical resistor values are 200K
at
VDD=3V.) When a pin outputs low, the resistor is disconnected regardless of a
RCR2 register bit being set.
Bit 5 thru bit 0 have open drain or CMOS output options, which are controlled by
the corresponding WOM2 register bits. These open drain or CMOS output options
may be selected for either the general purpose output ports or the peripheral
outputs (EVO, TCMP, and TDO).
7.4
PORT D
Port D pins serve one of two basic functions depending on the MCU mode
selected; LCD Frontplanes and Backplanes driver outputs, or general purpose
output pins. Since Port D is an output only port there is no DDRD register. In place
of DDRD is Port D MUX Control Register (PDMUX). Bits 7-4 of this register
control the Port/LCD muxing of Port D bits 7-4 respectively on a bit-wise basis.
These bits are cleared on reset, and writing a 1 to any bit will turn that pin into a
Port output. These outputs have the capability to drive 10 mA sink current when
(VOL
≤ Vss + 0.8V).
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