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參數(shù)資料
| 型號： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 126/165頁 |
| 文件大小： | 841K |
| 代理商： | MC68HC05PD6 |
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July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
CLOCK DISTRIBUTION
MOTOROLA
REV 1.1
8-3
8.3.2 XOSC On Line
If XOSC is the System Clock (SYS0:1=1:1), OSC can be stopped either by the
STOP instruction or by clearing the FOSCE bit.
The sub oscillator (XOSC) never stops except during power down. This clock may
also be used as the clock source of the system clock and Time Base.
8.3.2.1
XOSC with FOSCE=1
If the System Clock is XOSC and FOSCE=1, executing the STOP instruction will
halt OSC, put the MCU into a low power mode and clear the 6-bit POR counter.
The 7-bit divider is not initialized. Exiting STOP with external IRQ re-starts the
oscillator, however execution begins immediately using XOSC. When the POR
counter overows, FTUP is set signaling that OSC is stable and OSC can be used
as the System Clock. The stabilization time will vary between 7944 and 8072
counts.
8.3.2.2
XOSC with FOSCE=0
If XOSC is the System Clock, clearing FOSCE will stop OSC, and preset the 7-bit
divider and 6-bit POR counter to $0078. Execution will continue with XOSC and
when FOSCE is set again, OSC will re-start. When the POR counter overows,
FTUP is set signaling that OSC is stable and OSC can be used as the System
Clock. The stabilization time will be 8072 counts.
8.3.2.3
XOSC with FOSCE=0 and STOP
If XOSC is the System Clock and FOSCE is cleared, further power reduction can
be achieved by executing the STOP instruction. In this case OSC is stopped, the7-
bit divider and 6-bit POR counter is preset to $0078 (since FOSCE=0) and
execution is halted. Exiting STOP with external IRQ does not re-start the OSC,
however execution begins immediately using XOSC. OSC may be re-started by
setting FOSCE, and when the POR counter overows, FTUP will be set signaling
that OSC is stable and can be used as the System Clock. The stabilization time
will be 8072 counts.
8.3.2.4
STOP and WAIT Modes
During STOP mode the main oscillator (OSC) is shut down and the clock path
from the second oscillator (XOSC) is disconnected, such that all modules except
Time Base are halted. Entering STOP mode clears FTUP ag in the MISC
register, and initializes POR counter. The STOP mode is exited by RESET, PDI,
IRQ1, IRQ2, KWI, or RTC Interrupt.
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