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| 型號(hào)： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁(yè)數(shù)： | 9/165頁(yè) |
| 文件大?。?/td> | 841K |
| 代理商： | MC68HC05PD6 |
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GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC05PD6
11-4
REV 1.1
11.6
RECEIVE DATA IN (RDI)
Receive data in (RDI) is the serial data which is presented from the input pin via
the SCI to the receive data register (RDR). While waiting for a start bit, the
receiver samples the input at a rate 16 times higher than the set baud rate. This
increased rate is referred to as the RT rate. When the input (idle) line is detected
low, it is tested for three more sample times. If at least two of these three samples
detect a logic low, a valid start bit is assumed to be detected. If in two or more
samples, a logic high is detected, the line is assumed to be idle. The receive clock
generator is controlled by the baud rate register (see Section 11.9.5); however,
the SCI is synchronized by the start bit independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit, and the stop bit are
each sampled three times. The value of the bit is determined by voting logic, which
takes the value of a majority of samples. A noise ag is set when all three samples
on a valid start bit, data bit, or stop bit do not agree. A noise ag is also set when
the start verication samples do not agree.
11.7
START BIT DETECTION FOLLOWING A FRAMING ERROR
If there has been a framing error (FE) without detection of a break (10 zeros for 8-
bit format or 11 zeros for a 9-bit format), the circuit continues to operate as if there
actually were a stop bit, and the start edge will be placed articially. The last bit
received in the data shift register is inverted to a logic one, and the three logic-one
start qualiers (shown in Figure 11-4) are forced into the sample shift register
during the interval when detection of a start bit is anticipated (see Figure 11-5);
therefore, the start bit will be accepted no sooner than it is anticipated.
If the receiver detects that a break (RDRF=1, FE=1, receiver data register=$00)
produced the framing error, the start bit will not be articially induced, and the
receiver must actually receive a logic one before start. See Figure 11-6.
Figure 11-3. Sampling Technique used on All bits
RDI
previous bit
present bit
samples
next bit
VV
V
8
R
T
10
R
T
9
R
T
16
R
T
1
R
T
1
R
T
16
R
T
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