參數(shù)資料
型號(hào)： MC68HC05PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 143/165頁
文件大小： 841K
代理商： MC68HC05PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
TIMER SYSTEM
MOTOROLA
REV 1.1
9-7
Figure 9-5. Timer State Timing Diagram For Output Compare
$FFEB
$FFED
$FFEE
$FFEF
Internal Processor
Clock
T00
T01
T10
T11
Counter(16 Bit)
Output Compare
Flag (OC1F)
Internal
Timer
Clocks
1.
The CPU writes to the compare register may take place at any
time, but a compare only occurs at timer state T01. Thus, a 4-
cycle different may exist between the write to the compare
register and the actual compare.
2.
Internal compare takes place during timer state T01.
3.
OC1F is set at timer state T11 which follows the comparison
match
($FFED in this example).
$FFEC
Compare
Register
Compare
Register Latch
1
2
3
CPU writes $FFED
$FFED
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