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參數(shù)資料
| 型號： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 149/165頁 |
| 文件大小： | 841K |
| 代理商： | MC68HC05PD6 |
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GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
TIMER SYSTEM
MC68HC05PD6
9-12
REV 1.1
unintentionally be cleared if: 1)The timer status register is read or written when
TOF is set, and 2)The LSB of the free-running counter is read but not for the
purpose of servicing the ag. The counter alternate register at address $1A and
$1B contains the same value as the free-running counter (at address $18 and
$19); therefore, this alternate register can be read at any time without affecting the
timer overow ag in the timer status register.
9.1.6 Operation During Low Power Mode
During STOP and WAIT instructions, the programmable Timer 1 functions as
follows: during the wait mode, the Timer 1 continues to operate normally and may
generate an interrupt to trigger the CPU out of the wait state; during the STOP
mode, the Timer 1 holds at its current state, retaining all data, and resumes
operation from this point when external interrupt (IRQ), or internal interrupt is
received.
9.2
TIMER 2
Timer 2 is an 8-bit event counter which has one compare register, one event input
pin (EVI), and one event output pin (EVO). The event counter is clocked by the
external clock (EXCLK) or prescaled system clock (CLK2), selected by the T2CLK
bit in the TCR2 register. The EXCLK may be EVI direct or EVI gated by CLK2,
which is selected by the IM2 bit at the EVI block (refer to the EVI description).
Timer 2 may be used as a modulus clock divider with EVO pin, free running
counter (when compare register is $00), or periodic interrupt timer.
The Timer Counter 2 (CNT2) is an 8-bit up counter with preset input. The counter
is preset to $01 by a CMP2 signal from the comparator or by a CPU write to it that
is done while the system clock (PH2) is low.
The CLK2 from the prescaler or the EXTCLK from the EVI block are selected as
timer clock by the T2CLK bit in the TCR2 register. The CLK2 and the EXCLK are
synchronized to the falling edge of system clock in the prescaler and the EVI
blocks. The minimum pulse width of CLK2 is the same as the system clock, and
the minimum pulse width of EXCLK (event mode) is one PH2 cycle.
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