參數(shù)資料
型號： MC68HC05PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 11/165頁
文件大?。?/td> 841K
代理商： MC68HC05PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC05PD6
11-6
REV 1.1
11.8
TRANSMIT DATA OUT (TDO)
Transmit data out is the serial data which is presented from the internal data bus
via the SCI and then to the output pin. Data format is as discussed above and
shown in Figure 11-2. The transmitter generates a bit time by using a derivative of
the RT clock, thus producing a transmission rate equal to 1/16 that of the receiver
sample clock.
11.9
SCI REGISTERS
There are ve registers used in the SCI; the internal conguration of these
registers is discussed in the following paragraphs. A block diagram of the SCI
system is shown in Figure 11-1.
11.9.1 Serial Communications Data Register (SCDAT)
The serial communications data register performs two functions in the serial
communications interface; i.e. it acts as the receive data register when it is read
and as the transmit data register when it is written. Figure 11-1 shows this
register as two separate registers, namely: the receive data register (RDR) and
the transmit data register (TDR). As shown in Figure 11-1, the TDR (transmit data
register) provides the parallel interface from the internal data bus to the transmit
shift register and the receive data register (RDR) provides the interface from the
receive shift register to the internal data bus.
When SCDAT is read, it becomes the receive data register and contains the last
byte of data received. The receive data register, represented above, is a read-only
register containing the last byte of data received from the shift register for the
internal data bus. The RDRF bit (receive data register full bit in the serial
communications status register) is set to indicate that a byte has been transferred
from the input serial shift register to the serial communications data register. The
transfer is synchronized with the receiver bit rate clock (from the receive control)
as shown in Figure 11-1. All data is received least-signicant-bit rst.
When SCDAT is written, it becomes the transmit data register and contains the
next byte of data to be transmitted. The transmit data register, also represented
above, is a write-only register containing the next byte of data to be applied to the
X
7
XXXXXXX
6543210
W
R
SCDR
$000E
reset
SCD7
SCD6
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
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