參數(shù)資料
型號： MC68HC05PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 145/165頁
文件大?。?/td> 841K
代理商： MC68HC05PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
TIMER SYSTEM
MC68HC05PD6
9-8
REV 1.1
9.1.3 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are read-only
and are used to latch the value of the free-running counter after the corresponding
input capture edge detector senses a dened transition. The level transition which
triggers the counter transfer is dened by the corresponding input edge bit
(IEDG). Reset does not affect the contents of the input capture register.
The result obtained by an input capture will be one more than the value of the
free-running counter on the rising edge of the internal bus clock preceding the
external transition. This delay is required for internal synchronization. Resolution
is one count of the free-running counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on
each proper signal transition regardless of whether the input capture ag (ICF) is
set or clear. The input capture register always contains the free-running counter
value that corresponds to the most recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer is
inhibited until the LSB ($15) is also read. This characteristic causes the time used
in the input capture software routine and its interaction with the main program to
determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus clock.
NOTE
Since the TCAP pin is shared with the PC3 I/O pin, changing the
state of the PC3 DDR or Data Register can cause an unwanted
TCAP interrupt. This can be handled by clearing the ICIE bit before
changing the conguration of PC3, and clearing any pending
interrupts before enabling ICIE.
X
7
XXXXXXX
6543210
W
R
ICAPH
$0014
reset
IC15
IC14
IC13
IC12
IC11
IC10
IC9
IC8
X
7
XXXXXXX
6543210
W
R
ICAPL
$0015
reset
IC7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
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