- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45222 > MC68HC05PD6 (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC05PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 17/165頁 |
| 文件大小： | 841K |
| 代理商： | MC68HC05PD6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
REV 1.1
11-11
IDLE
When the idle line detect bit is set, it indicates that a receiver idle line is
detected (receipt of a minimum number of ones to constitute the number of bits
in the byte format). The minimum number of ones needed will be 10 (M=0) or
11 (M=1). This allows a receiver that is not in the wake-up mode to detect the
end of a message, detect the preamble of a new message, or to resynchronize
with the transmitter. The IDLE bit is cleared by accessing the serial
communications status register (with IDLE set) followed by a read of the serial
communications data register. The IDLE bit will not be set again until after an
RDRF has been set; i.e., a new idle line occurs. The IDLE is not set by an idle
line when the receiver “wakes up” from the wake-up mode. Reset clears the
IDLE bit.
OR
When the overrun error bit is set, it indicates that the next byte is ready to be
transferred from the receive shift register to the serial communications data
register when it is already full (RDRF it is set). Data transfer is then inhibited
until the RDRF bit is cleared. Data in the serial communications data register is
valid in this case, but additional data received during an overrun condition
(including the byte causing overrun) will be lost. The OR bit is cleared when the
serial communications status register is accessed (with OR set), followed by a
read of the serial communications data register. Reset clears the OR bit.
NF
The noise ag bit is set if there is noise on a “valid” start bit or if there is noise
on any of the data bits or if there is noise on the stop bit. It is not set by noise on
the idle line nor by invalid (false) start bits. If there is noise, the NF bit is not set
until the RDRF ag is set. Each data bit is sampled three times as described
above in RECEIVE DATA IN and shown in Fig. 5-3. The NF bit represents the
status of the byte in the serial communications data register. For the byte being
received (shifted in) there will also be a “working” noise ag the value of which
will be transferred to the NF bit when the serial data is loaded into the serial
communications data register. The NF bit does not generate an interrupt
because the RDRF bit gets set with NF and can be used to generate the
interrupt. The NF bit is cleared when the serial communications status register
is accessed (with NF set), followed by a read of the serial communications data
register. Reset clears the NF bit.
FE
The framing error bit is set when the byte boundaries in the bit stream are not
synchronized with the receiver bit counter (generated by a “l(fā)ost” stop bit). The
byte is transferred to the serial communications data register and the RDRF bit
is set. The FE bit does not generate an interrupt because the RDRF bit is set at
the same time as FE and can be used to generate the interrupt. Note that if the
byte received causes a framing error and it will also cause an overrun if
transferred to the serial communications data register, then the overrun bit will
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC705PD6 | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| MC68HC05PE0P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05PE0CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05PL4CSD | 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705PL4BDW | 8-BIT, OTPROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05PV8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05PV8A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05RC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16FN | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。