參數(shù)資料
型號(hào)： MC68HC05PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 12/165頁
文件大小： 841K
代理商： MC68HC05PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
REV 1.1
11-7
transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the serial communications data register is transferred to
the transmit shift register (after the current byte in the shift register has been
transmitted). The transfer from the SCDAT to the transmit shift register is
synchronized with the bit rate clock (from the transmit control) as shown in
Figure 11-1. All data is transmitted least-signicant-bit rst.
11.9.2 Serial Communications Control Register 1 (SCCR1)
The serial communications control register 1 (SCCR1) provides the control bits
which: 1) determine the word length (either 8 or 9 bits), and 2) selects the method
used for the wake-up feature. Bits 6 and 7 provide a location for storing the ninth
bit for longer bytes.
R8
If the M bit is a one, then this bit provides a storage location for the ninth bit in
the receive data byte. Reset does not affect this bit.
T8
If the M bit is a one, then this bit provides a storage location for the ninth bit in
the transmit data byte. Reset does not affect this bit.
M
The option of the word length is selected by the conguration of this bit and is
shown below. Reset does not affect this bit.
0 =
1 start bit, 8 data bits, 1 stop bit
1 =
1 start bit, 9 data bits, 1 stop bit
WAKE
This bit allows the user to select the method for receive “wake up”. If the WAKE
bit is a logic zero, an idle line condition will “wake up” the receiver. If the WAKE
bit is set to a logic one, the system acknowledges an address bit (most
signicant bit). The address bit is dependent on both the WAKE bit and the M
bit level (table shown below). (Additionally, the receiver does not use the wake-
up feature unless the RWU control bit in serial communications control register
2 is set as discussed below.) Reset does not affect this bit.
X
7
X-X
X-
-
6543210
W
R
SCCR1
$000B
reset
R8
T8
M
WAKE
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