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參數(shù)資料
| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 98/145頁 |
| 文件大小： | 829K |
| 代理商： | EC000UM |
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Bus Operation
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
3-15
STATE 2
On the rising edge of state 2 (S2), the SCM68000 asserts ASB, UDSB or LDSB, and DSB.
STATE 3
During state 3 (S3), no bus signals are altered.
STATE 4
During state 4 (S4), the SCM68000 waits for a cycle termination signal (DTACKB or
BERRB). If neither termination signal is asserted before the falling edge at the end of S4,
the SCM68000 inserts wait states (full clock cycles) until either DTACKB or BERRB is as-
serted. See 3.7 The Relationship of DTACKB, BERRB, and HALTIB for a description
of how DTACKB and BERRB interact.
CASE READ 1: Only DTACK is received.
STATE 5
During state 5 (S5), no bus signals are altered.
STATE 6
During state 6 (S6), data from the device is driven onto the data bus.
STATE 7
On the falling edge of the clock entering state 7 (S7), the SCM68000 accepts data from
the device and negates UDSB or LDSB, and DSB. The device negates DTACKB at this
time.
STATES 8–11
The bus signals are unaltered during state 8 (S8)through state 11 (S11), during which the
arithmetic logic unit makes appropriate modifications to the data.
STATE 12
The write portion of the cycle starts in state 12 (S12). The valid function codes on FC2–
FC0, the address bus lines, ASB, RWB, and ERWB remain unaltered.
STATE 13
During state 13 (S13), ERWB is driven to a logic low.
STATE 14
On the rising edge of state 14 (S14), the SCM68000 drives RWB to a logic low.
STATE 15
During state 15 (S15), the data bus is driven out of the high-impedance state as data is
placed on the bus.
STATE 16
During state 16 (S16), the SCM68000 waits for a cycle termination signal (DTACKB or
BERRB). If neither termination signal is asserted before the falling edge at the end of S16,
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