參數(shù)資料
型號： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 89/145頁
文件大?。?/td> 829K
代理商： EC000UM
Bus Operation
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
3-7
STATE 1
Entering state 1 (S1), TSCAE is driven low to indicate the beginning of the bus cycle.
STATE 2
On the rising edge of state 2 (S2), the SCM68000 asserts ASB, UDSB, LDSB, and DSB.
STATE 3
During state 3 (S3), no bus signals are altered.
STATE 4
During state 4 (S4), the SCM68000 waits for a cycle termination signal (DTACKB or
BERRB) If neither termination signal is asserted before the falling edge at the end of S4,
the SCM68000 inserts wait states (full clock cycles) until either DTACKB or BERRB is as-
of how DTACKB and BERRB interact.
CASE 1: DTACKB is received alone or with BERRB (see 3.4 Bus Error and Halt Opera-
STATE 5
During state 5 (S5), no bus signals are altered.
STATE 6
Sometime between state 2 (S2) and state 6 (S6), data from the device is driven onto the
data bus.
STATE 7
On the falling edge of the clock entering state 7 (S7), the SCM68000 latches data from
the addressed device and negates ASB, UDSB, LDSB, and DSB. The device negates
DTACKB or BERRB at this time.
CASE 2: BERRB is received without DTACKB (see 3.4 Bus Error and Halt Operation).
STATE 5
During state 5 (S5), no bus signals are altered.
STATE 6
During state 6 (S6), no bus signals are altered.
STATE 7
During state 7 (S7), no bus signals are altered.
STATE 8
During state 8 (S8), no bus signals are altered.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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