
8-Bit Instruction Execution Times
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
5-7
5.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES
Table 5-11 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective
address (LEA), push effective address (PEA), and move multiple registers (MOVEM)
instructions. The total number of clock periods, the number of read cycles, and the number
of write cycles are shown in the previously described format.
5.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES
Table 5-12 lists the timing data for multiprecision instructions. The numbers of clock periods
include the times to fetch both operands, perform the operations, store the results, and read
the next instructions. The total number of clock periods, the number of read cycles, and the
number of write cycles are shown in the previously described format.
Table 5-10. Conditional Instruction Execution Times
Instruction
Displacement
Trap or Branch
Taken
Trap or Branch
Not Taken
Bcc
Byte
Word
18(4/0)
12(2/0)
20(4/0)
BRA
Byte
Word
18(4/0)
—
BSR
Byte
Word
34(4/4)
—
DBcc
cc True
cc False
—
18(4/0)
20(4/0)
26(6/0)
CHK
—
68(8/6)+*
14(2/0)+
TRAPV
—
66(10/6)
8(2/0)
+ Add effective address calculation time for word operand.
* Indicates maximum base value.
Table 5-11. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times
Instruction
Size
(An)
(An)+
–(An)
(d16,An) (d8,An,Xn)+ (xxx).W
(xxx).L
(d16 PC)
(d8, PC,
Xn)*
JMP
—
16(4/0)
—
18(4/0)
22(4/0)
18(4/0)
24(6/0)
18(4/0)
22(4/0)
JSR
—
32(4/4)
—
34(4/4)
38(4/4)
34(4/4)
40(6/4)
34(4/4)
32(4/4)
LEA
—
8(2/0)
—
16(4/0)
20(4/0)
16(4/0)
24(6/0)
16(4/0)
20(4/0)
PEA
—
24(2/4)
—
32(4/4)
36(4/4)
32(4/4)
40(6/4)
32(4/4)
36(4/4)
MOVEM
M
→ R
Word
Long
24+8n
(6+2n/0)
24+8n
(6+2n/0)
—
32+8n
(8+2n/0)
34+8n
(8+2n/0)
32+8n
(10+n/0)
40+8n
(10+2n/0)
32+8n
(8+2n/0)
34+8n
(8+2n/0)
24+16n
(6+4n/0)
24+16n
(6+4n/0)
32+16n
(8+4n/0)
34+16n
(8+4n/0)
32+16n
(8+4n/0)
40+16n
(8+4n/0)
32+16n
(8+4n/0)
34+16n
(8+4n/0)
MOVEM
R
→ M
Word
Long
16+8n
(4/2n)
—
16+8n
(4/2n)
24+8n
(6/2n)
26+8n
(6/2n)
24+8n
(6/2n)
32+8n
(8/2n)
—
16+16n
(4/4n)
16+16n
(4/4n)
24+16n
(6/4n)
26+16n
24+16n
(8/4n)
32+16n
(6/4n)
*The size of the index register (Xn) does not affect the instruction's execution time.
n is the number of registers to move.
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