參數(shù)資料
型號(hào)： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊(cè)（SCM68000）
文件頁(yè)數(shù)： 101/145頁(yè)
文件大?。?/td> 829K
代理商： EC000UM
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Bus Operation
3-18
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
3.2.1 Requesting the Bus
External devices capable of becoming bus masters assert BRB to request the bus. This sig-
nal can be ORed (not necessarily constructed from open-collector devices) from any of the
devices in the system that can become bus master. The SCM68000, which is at a lower bus
priority level than the external devices, relinquishes the bus after it completes the current
bus cycle.
When no acknowledge is received before the bus request signal is negated, the SCM68000
continues to use the bus. Also, BGACKB allows arbitration time for another bus master to
be overlapped with bus cycles to lessen bus idle time.
3.2.2 Receiving the Bus Grant
After BRB is asserted, the SCM68000 asserts BGB immediately following internal synchro-
nization. The exception to this is when the SCM68000 has made an internal decision to exe-
cute the next bus cycle but has not yet asserted ASB for that cycle. In this case, BGB is
delayed until ASB is asserted to indicate to external devices that a bus cycle is in progress.
Figure 3-14. 3-Wire Bus Arbitration Cycle Flowchart
GRANT BUS ARBITRATION
REQUEST THE BUS
1) ASSERT BUS REQUEST (BRB)
REQUESTING DEVICE
1) EXTERNAL ARBITRATION DETER-
MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACKB)
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BRB
TERMINATE ARBITRATION
1) NEGATE BGACKB
PROCESSOR
1) ASSERT BUS GRANT (BGB)
ACKNOWLEDGE BUS MASTERSHIP
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ
AND WRITE CYCLES) ACCORDING
TO THE SAME RULES THE PRO-
CESSOR USES
REARBITRATE OR RESUME
PROCESSOR OPERATION
RELEASE BUS MASTERSHIP
1) NEGATE BGB (AND WAIT FOR BGACKB
TO BE NEGATED)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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