參數(shù)資料
型號： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 21/145頁
文件大?。?/td> 829K
代理商： EC000UM
8-Bit Instruction Execution Times
5-8
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
The following notation applies in Table 5-12:
Dn — Data register operand
M — Memory operand
5.11 MISCELLANEAOUS INSTRUCTION EXECUTION TIMES
Table 5-13 and Table 5-14 list the timing data for miscellaneous instructions. The total num-
ber of clock periods, the number of read cycles, and the number of write cycles are shown
in the previously described format. The number of clock periods, the number of read cycles,
and the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 5-12. Multiprecision Instruction Execution Times
Instruction
Size
op Dn, Dn
op M, M
ADDX
Byte
Word
Long
8(2/0)
12(2/0)
22(4/1)
50(6/2)
58(10/4)
CMPM
Byte
Word
Long
—
16(4/0)
24(6/0)
40(10/0)
SUBX
Byte
Word
Long
8(2/0)
12(2/0)
22(4/1)
50(6/2)
58(10/4)
ABCD
Byte
10(2/0)
20(4/1)
SBCD
Byte
10(2/0)
20(4/1)
Table 5-13. Miscellaneous Instruction Execution Times
Instruction
Register
Memory
ANDI to CCR
32(6/0)
—
ANDI to SR
32(6/0)
—
EORI to CCR
32(6/0)
—
EORI to SR
32(6/0)
—
EXG
10(2/0)
—
EXT
8(2/0)
—
LINK
32(4/4)
—
MOVE to CCR
18(4/0)
18(4/0)+
MOVE to SR
18(4/0)
18(4/0)+
MOVE from SR
10(2/0)
16(2/2)+
MOVE to USP
8(2/0)
—
MOVE from USP
8(2/0)
—
NOP
8(2/0)
—
ORI to CCR
32(6/0)
—
ORI to SR
32(6/0)
—
RESET
136(2/0)
—
RTE
40(10/0)
—
RTR
40(10/0)
—
RTS
32(8/0)
—
STOP
4(0/0)
—
SWAP
8(2/0)
—
UNLK
24(6/0)
—
+ Add effective address calculation time for word operand.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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