參數(shù)資料
型號： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 96/145頁
文件大小： 829K
代理商： EC000UM
Bus Operation
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
3-13
STATE 9
During state 9 (S9), ASB, UDSB, LDSB, and DSB are negated. The device negates
BERRB at this time. At the end of S9, the data bus is placed in the high-impedance state,
and RWB and ERWB are driven to a logic high.
3.1.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read operation, modifies the data in the arithmetic
logic unit, and writes the data back to the same address. The address strobe (ASB) remains
asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS)
instruction uses this cycle to provide a signaling capability without deadlock between pro-
cessors in a multiprocessing environment. The TAS instruction (the only instruction that
uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write cycles
are byte operations. The read-modify-write flowchart is shown in Figure 3-12 and the timing
diagram is shown in Figure 3-13.
Figure 3-12. Read-Modify-Write Cycle Flowchart
BUS MASTER
ADDRESS THE DEVICE
1) SET RWB AND ERWB TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A31–A0
4) ASSERT ADDRESS STROBE (ASB)
5) ASSERT UPPER DATA STROBE (UDSB)
OR LOWER DATA STROBE (LDSB)
AND DATA STROBE (DSB)
6) ASSERT RMCB
TERMINATE THE CYCLE
OUTPUT THE DATA
1) DECODE ADDRESS
2) PLACE DATA ON D7–D0 OR D15–D8
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACKB)
SLAVE
START NEXT CYCLE
1) REMOVE DATA FROM D7–D0
OR D15–D8
2) NEGATE DTACKB
1) LATCH DATA
1) NEGATE UDSB AND LDSB
2) START DATA MODIFICATION
ACQUIRE THE DATA
START OUTPUT TRANSFER
1) SET RWB AND ERWB TO WRITE
2) PLACE DATA ON D7–D0 OR D15–D8
3) ASSERT UPPER DATA STROBE (UDSB)
OR LOWER DATA STROBE (LDSB)
AND DATA STROBE (DSB)
TERMINATE OUTPUT TRANSFER
1) NEGATE UDSB AND LDSB
2) NEGATE ASB
3) REMOVE DATA FROM D7–D0 OR
D15–D8
4) SET RWB AND ERWB TO READ
INPUT THE DATA
1) STORE DATA ON D7–D0 OR D15–D8
2) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACKB)
TERMINATE THE CYCLE
1) NEGATE DTACKB
5) NEGATE RMCB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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