參數(shù)資料
型號: EC000UM
英文描述: EC000 Core User's Manual (SCM68000)
中文描述: EC000核心用戶手冊(SCM68000)
文件頁數(shù): 42/145頁
文件大?。?/td> 829K
代理商: EC000UM
Electrical Characteristics
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
7-7
7.8 AC ELECTRICAL SPECIFICATIONS—BUS ARBITRATION
(Frequency = 0 to 20 MHz; GND = 0 Vdc, TA = TL to TH; see Figure 7-5 through Figure 7-8)
Num
Characteristic
3.3 V
5.0 V
Unit
Min
Max
Min
Max
7
Clock High to Address, Data Bus High Impedance (Maximum)
25
20
ns
33
Clock High to BGB Asserted
0
25
0
25
ns
34
Clock High to BGB Negated
0
25
0
25
ns
35
BRB Asserted to BGB Asserted
1.5
3.5
1.5
3.5
Clks
361
BRB Negated to BGB Negated
1.5
3.5
1.5
3.5
Clks
37
BGACKB Asserted to BGB Negated
1.5
3.5
1.5
3.5
Clks
37A2,4 BGACKB Asserted to BRB Negated
10 ns
1.5 Clks
10 ns
1.5 Clks
38
BGB Asserted to Control, Address, Data Bus High Impedance
(ASB Negated)
—42—42
ns
39
BGB Width Negated
1.5
1.5
Clks
46
BGACKB Width Low
1.5
1.5
Clks
47
Asynchronous Input Setup Time
5—5—
ns
57
BGACKB Negated to ASB, DSB, RWB Driven
1.5
1.5
Clks
57A
BGACKB Negated to FC Driven
1—1—
Clks
583
BRB Negated to ASB, DSB, RWB Driven
1.5
1.5
Clks
58A3
BRB Negated to FC Driven
1—1—
Clks
NOTES:
1.Setup time for the synchronous inputs BGACKB, IPLB2–IPLB0, and AVECB guarantees their recognition at the next
falling edge of the clock.
2.BRB need fall at this time only in order to insure being recognized at the end of the bus cycle.
3.The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting
BGACKB.
4.The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be
reasserted.
Figure 7-5. Bus Arbitration Timing Diagram
37A
37
46
36
39
34
38
33
35
CLKI
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERRB, BGACKB, BRB, DTACKB,
IPLB2–IPLB0, and AVECB guarantees their recognition at the next falling edge of the clock.
BRB
BGACKB
BGB
AND RWB
STROBES
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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