參數(shù)資料
型號(hào)： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊(cè)（SCM68000）
文件頁數(shù)： 28/145頁
文件大?。?/td> 829K
代理商： EC000UM
16-Bit Instruction Execution Times
6-4
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
6.4 IMMEDIATE INSTRUCTION EXECUTION TIMES
The numbers of clock periods listed in Table 6-5 include the times to fetch immediate oper-
ands, perform the operations, store the results, and read the next operation. The total num-
ber of clock periods, the number of read cycles, and the number of write cycles are shown
in the previously described format. The number of clock periods, the number of read cycles,
and the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
In Table 6-5, the following notation applies:
# — Immediate operand
Dn — Data register operand
An — Address register operand
M — Memory operand
Table 6-4. Standard Instruction Execution Times
Instruction
Size
op<ea>, An
op<ea>, Dn
op Dn, <M>
ADD/ADDA
Byte, Word
Long
8(1/0)+
6(1/0)+**
4(1/0)+
6(1/0)+**
8(1/1)+
12(1/2)+
AND
Byte, Word
Long
—
4(1/0)+
6(1/0)+**
8(1/1)+
12(1/2)+
CMP/CMPA
Byte, Word
Long
6(1/0)+
4(1/0)+
6(1/0)+
—
DIVS
DIVU
Word
—
158(1/0)+*
140(1/0)+*
—
EOR
Byte, Word
Long
—
4(1/0)***
8(1/0)***
8(1/1)+
12(1/2)+
MULS
MULU
Word
—
70(1/0)+*
—
OR
Byte, Word
Long
—
4(1/0)+
6(1/0)+**
8(1/1)+
12(1/2)+
SUB
Byte, Word
Long
8(1/0)+
6(1/0)+**
4(1/0)+
6(1/0)+**
8(1/1)+
12(1/2)+
+Add effective address calculation time.
Word or long only.
*Indicates maximum basic value added to word effective address time.
**The base time of six clock periods is increased to eight if the effective address mode is register
direct or immediate (effective address time should also be added).
***Only available effective address mode is data register direct.
MULS, MULU—The multiply algorithm requires 38+2n clocks where n is dened as:
MULU: n = the number of ones in the <ea>
MULS: n=concatenate the <ea> with a zero as the LSB; n is the resultant number of 10 or 01
patterns in the 17-bit source; i.e., worst case happens when the source is $5555.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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