參數(shù)資料
型號(hào)： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 31/145頁
文件大?。?/td> 829K
代理商： EC000UM
16-Bit Instruction Execution Times
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
6-7
6.8 CONDITIONAL INSTRUCTION EXECUTION TIMES
Table 6-9 lists the timing data for the conditional instructions. The total number of clock peri-
ods, the number of read cycles, and the number of write cycles are shown in the previously
described format.
6.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES
Table 6-10 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective
address (LEA), push effective address (PEA), and move multiple registers (MOVEM)
instructions. The total number of clock periods, the number of read cycles, and the number
of write cycles are shown in the previously described format.
6.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES
Table 6-11 lists the timing data for multiprecision instructions. The number of clock periods
includes the time to fetch both operands, perform the operations, store the results, and read
the next instructions. The total number of clock periods, the number of read cycles, and the
number of write cycles are shown in the previously described format.
Table 6-9. Conditional Instruction Execution Times
Instruction
Displacement
Branch Taken
Branch Not Taken
Bcc
Byte
Word
10(2/0)
8(1/0)
12(2/0)
BRA
Byte
Word
10(2/0)
—
BSR
Byte
Word
18(2/2)
—
CHK (No Trap)
—
10(1/0)+
—
DBcc
cc true
cc false
—
10(2/0)
12(2/0)
14(3/0)
TRAPV
—
4(1/0)
—
Table 6-10. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times
Instruction Size
(An)
(An)+
–(An) (d16,An) (d8,An,Xn)+ (xxx).W
(xxx).L
(d16 PC)
(d8, PC, Xn)*
JMP
—
8(2/0)
—
10(2/0)
14(3/0)
10(2/0)
12(3/0)
10(2/0)
14(3/0)
JSR
—
16(2/2)
—
18(2/2)
22(2/2)
18(2/2)
20(3/2)
18(2/2)
22(2/2)
LEA
—
4(1/0)
—
8(2/0)
12(2/0)
8(2/0)
12(3/0)
8(2/0)
12(2/0)
PEA
—
12(1/2)
—
16(2/2)
20(2/2)
16(2/2)
20(3/2)
16(2/2)
20(2/2)
MOVEM
M
→ R
Word
Long
12+4n
(3+n/0)
12+4n
(3+n/0)
—
16+4n
(4+n/0)
18+4n
(4+n/0)
16+4n
(4+n/0)
20+4n
(5+n/0)
16+4n (4n/0) 18+4n (4+n/0)
12+8n
(3+2n/
0)
12+8n
(3+n/0)
16+8n
(4+2n/0)
18+8n
(4+2n/0)
16+8n
(4+2n/0)
20+8n
(5+2n/0)
16+8n
(4+2n/0)
18+8n (4+2n/0)
MOVEM
R
→ M
Word
Long
8+4n
(2/n)
—
8+4n
(2/n)
12+4n
(3/n)
14+4n
(3/n)
12+4n
(3/n)
16+4n
(4/n)
—
8+8n
(2/2n)
8+8n
(2/2n)
12+8n
(3/2n)
14+8n
(3/2n)
12+8n
(3/2n)
16+8n
(4/2n)
n is the number of registers to move.
*The size of the index register (Xn) does not affect the instruction's execution time.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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