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| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 75/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Signal Description
2-6
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
the interrupt is recognized. Table 2-5 lists the interrupt levels, the states of IPLB2–IPLB0 that
define each level, and the mask value that allows an interrupt at each level.
2.7 SYSTEM CONTROL
The system control inputs are used to reset, halt, disable, and test the SCM68000 as well
as signal a bus error to the SCM68000 and choose either the 8-bit or 16-bit mode. The two
outputs reset the external devices in the system and signal to those devices when the
SCM68000 has stopped executing instructions because of an error. The system control sig-
nals are described in the following paragraphs.
2.7.1 Bus Error (BERRB)
This input signal indicates a problem in the current bus cycle. The problem may be the fol-
lowing:
1. No response from a device.
2. No interrupt vector number returned.
3. An illegal access request rejected by a memory management unit.
4. Some other application-dependent error.
The SCM68000 either retries the bus cycle or performs exception processing, as deter-
mined by interaction between the bus error signal and the halt signal.
2.7.2 Reset External/Internal (RESETIB, RESETOB)
The assertion of the active-low input, RESETIB can start a system initialization sequence by
resetting the SCM68000. The SCM68000 assertion of RESETOB (from executing a RESET
instruction) resets all external devices of a system without affecting the internal state of the
SCM68000. The interaction of RESETIB, RESETOB, and HALTIB is described in 4.3.1
Reset.
2.7.3 Halt External/Internal (HALTIB, HALTOB)
Asserting the active-low input, HALTIB causes the SCM68000 to stop bus activity at the
completion of the current bus cycle. This operation places all control signals in the inactive
state and places the data bus in a high-impedance state (see Table 2-1).
Table 2-5. Interrupt Levels and Mask Values
Requested
Interrupt Level
Control Line Status
Interrupt Mask Level
Required for Recognition
IPLB2
IPLB1
IPLB0
0
High
No Interrupt Is Requested
1
High
Low
0
2
High
Low
High
1–0
3
High
Low
2–0
4
Low
High
3–0
5
Low
High
Low
4–0
6
Low
High
5–0
7
Low
7–0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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