- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97874 > EC000UM EC000 Core User＇s Manual (SCM68000) PDF資料下載
參數(shù)資料
| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 5/145頁 |
| 文件大小： | 829K |
| 代理商： | EC000UM |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁
Exception Processing
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
4-17
registers are affected by a RESET instruction. Figure 4-12 shows a timing diagram for
RESETOB.
NOTE
The user must ensure that all external devices are reset at the
completion of the RESET instruction. The RESETOB signal is
negated on the rising edge of S0 of the next bus cycle.
If the RESETIB and RESETOB signals are connected as shown in Figure 4-10, the HALTIB
signal should not be asserted during the RESET instruction. When the SCM68000 recog-
nizes that both the HALTIB and RESETIB signals are asserted, it will begin the reset excep-
tion and negate RESETOB which will cause RESETIB to be negated. Since RESETIB would
not be asserted for at least ten clock periods with HALTIB, a partial reset will occur and may
drive the SCM68000 into an unknown state.
4.3.1.1.3 Reset Using Only RESETIB. The SCM68000 must initially be reset using the
RESETIB and HALTIB signals as previously described. However, subsequent resets can
also be accomplished by asserting only the RESETIB signal for a minimum of 132 clock peri-
ods.
Because an assertion of the RESETIB signal is ignored while the RESETOB signal is
asserted, the two signals can be connected as shown in Figure 4-10. Since the core may be
executing a RESET instruction at the time it is being reset using only the RESETIB signal,
the RESETIB signal should be asserted for a minimum of 132 clock periods. This will ensure
that the RESETOB signal has been negated and the RESETIB signal will be recognized.
Figure 4-11. Reset Operation Timing Diagram
T 4 CLOCKS
Note 2
Note 3
Note 4
Note 5
Note 6
NOTES
1. Internal start-up time
2. SSP high read in here
3. SSP low read in here
4. PC High read in here
5. PC Low read in here
6. First instruction fetched here
Bus State Unknown:
All Control Signals Inactive.
All Three-State Signals in the
High-Impedance State.
CLKI
VCC
RESETIB
HALTIB
BUS CYCLES
<
T
≥ 132 CLOCK PERIODS
Note1
FOR 16-BIT MODE:
VDD
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EC103B | Sensitive SCRs |
| EC103B1 | Sensitive SCRs |
| EC103B2 | Sensitive SCRs |
| EC103B3 | Sensitive SCRs |
| EC103D175 | Thyristor Product Catalog |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EC0010-000 | 制造商:TE Connectivity 功能描述:EC0010-000 |
| EC001031 | 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Header, Nominal current: 12 A, Rated voltage (III/2): 320 V, Assembly: Soldering |
| EC001121 | 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 4, Pitch: 5mm, Connection method: Screw connection, Color: Black, Contact surface: Tin |
| EC001283 | 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 7, Pitch: 5.08 mm, Connection method: Solder/Slip-on connection, Color: green, Contact surface: Tin, Assembly: Direct mounting |
| EC0013-000 | 制造商:TE Connectivity 功能描述:EC0013-000 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。