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| 型號(hào)： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊(cè)（SCM68000） |
| 文件頁(yè)數(shù)： | 102/145頁(yè) |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
vii
TABLE OF CONTENTS
Section 1
Overview
1.1
FlexCore Integrated Processors ................................................................... 1-2
1.1.1
FlexCore Advantages ................................................................................. 1-4
1.1.2
FlexCore Module Types.............................................................................. 1-4
1.2
Development Cycle....................................................................................... 1-5
1.3
Programming Model...................................................................................... 1-7
1.4
Data Types and Addressing Modes.............................................................. 1-9
1.5
Data Organization ....................................................................................... 1-10
1.5.1
Data Registers .......................................................................................... 1-10
1.5.2
Address Registers .................................................................................... 1-10
1.5.3
Data Organization In Memory ................................................................... 1-10
1.6
Instruction Set Summary............................................................................. 1-11
Section 2
Signal Description
2.1
Address Bus (A31–A0) ................................................................................. 2-1
2.2
Data Bus (D15–D0)....................................................................................... 2-1
2.3
Clock (CLKI, CLKO)...................................................................................... 2-1
2.4
Asynchronous Bus Control ........................................................................... 2-3
2.4.1
Address Strobe (ASB) ................................................................................ 2-3
2.4.2
Read/Write (RWB) and Early Read/Write (ERWB)..................................... 2-3
2.4.3
Upper and Lower Data Strobes (UDSB, LDSB), and Data Strobe (DSB) .. 2-4
2.4.4
Data Transfer Acknowledge (DTACKB) ..................................................... 2-4
2.4.5
Data Transfer Size (SIZ1–SIZ0) ................................................................. 2-4
2.4.6
Read-Modify-Write (RMCB) ........................................................................ 2-5
2.5
Bus Arbitration Control.................................................................................. 2-5
2.5.1
Bus Request (BRB) .................................................................................... 2-5
2.5.2
Bus Grant (BGB)......................................................................................... 2-5
2.5.3
Bus Grant Acknowledge (BGACKB)—3-Wire Protocol Only ...................... 2-5
2.6
Interrupt Control (IPLB2–IPLB0) ................................................................... 2-5
2.7
System Control ............................................................................................. 2-6
2.7.1
Bus Error (BERRB) ..................................................................................... 2-6
2.7.2
Reset External/Internal (RESETIB, RESETOB) ......................................... 2-6
2.7.3
Halt External/Internal (HALTIB, HALTOB) .................................................. 2-6
2.7.4
Mode (MODE)............................................................................................. 2-7
2.7.5
Disable Control (DISB) ............................................................................... 2-7
2.7.6
Test Mode (TEST) ...................................................................................... 2-7
2.7.7
Test Clock (TESTCLK) ............................................................................... 2-7
2.7.8
Autovector (AVECB) ................................................................................... 2-8
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