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| 型號(hào)： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 76/145頁 |
| 文件大小： | 829K |
| 代理商： | EC000UM |
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Signal Description
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
2-7
When the SCM68000 has stopped executing instructions (in the case of a double bus fault
condition, for example), the active-low output, HALTOB, is asserted by the SCM68000 to
indicate the condition to external devices.
2.7.4 Mode (MODE)
This input selects between the 8-bit and 16-bit operating modes. If this input is grounded
during reset, the SCM68000 comes out of reset in the 8-bit mode. If this input is tied to a
logic high during reset, the SCM68000 comes out of reset in the 16-bit mode. Changing this
input during normal operation may produce unpredictable results.
2.7.5 Disable Control (DISB)
This active-low signal is designed to place the SCM68000 into a quiescent state allowing
other sections of the circuit to be tested without interference from the SCM68000. When this
signal is asserted, the SCM68000 responds with the following with minimum gate delay if
the clock is stopped:
All three-state outputs will be placed into a high-impedance state.
The bus grant (BGB), clock output (CLKO), halt output (HALTOB), reset output (RESE-
TOB), microsequencer status (STATUSB), stop instruction indicator (STOP), and test
clock (TESTCLK) signals remain at the state they were in when the clock was stopped.
The remaining outputs are disabled, forcing them into an inactive state.
If the clock is running, the SCM68000 responds with the following with minimum gate delay:
All three-state outputs will be placed into a high-impedance state.
The clock output (CLKO) continues to follow the clock input (CLKI).
The microsequencer status (STATUSB) signal is forced to a logic low.
The test clock (TESTCLK) signal is forced to a logic low.
The remaining outputs are disabled, forcing them into their inactive states.
When DISB is asserted, it is internally gated with the internal SCM68000 reset and halt
signals after the input synchronizer. The user must ensure that the system is reset as dis-
cussed in 4.3.1 Reset.
2.7.6 Test Mode (TEST)
This active-high input signal allows the SCM68000 to enter the test mode. This permits
application of standard M68000 family test mode patterns to the SCM68000.
2.7.7 Test Clock (TESTCLK)
If the SCM680000 is properly reset during simulation, the TESTCLK signal will begin to
pulse. A single period of the test clock consists of ten SCM68000 clock periods (six clocks
low, four clocks high). This signal is generated by an internal ring counter that may come up
in any state. (At power-on, it is impossible to guarantee phase relationship of TESTCLK to
CLKI.) The TESTCLK signal is a free-running clock that runs regardless of the state of the
MPU bus. For more information on resetting the SCM68000 for simulation, see 4.3.1.2 Ini-
tializing the SCM68000 for Simulation.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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