參數(shù)資料
型號： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 100/145頁
文件大小： 829K
代理商： EC000UM
Bus Operation
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
3-17
STATE 11
During state 11 (S11), ASB, is negated. The cycle terminates without the write portion of
the cycle.
CASE WRITE 2: Only BERRB is received (see 3.4 Bus Error and Halt Operation).
STATES 17–20
The bus signals are unaltered during state 17 (S17) through state 20 (S20).
STATE 21
During state 21 (S21), the SCM68000 negates ASB, UDSB or LDSB, and DSB.
RMCB is driven to a logic high after ASB is negated and before the falling edge of S1 of the
next bus cycle. However, the value of RMCB is not guaranteed between bus cycles after
ASB is negated for the cases described in this section.
3.2 BUS ARBITRATION
Bus arbitration is a technique used by bus master devices to request, to be granted, and to
acknowledge bus mastership. Bus arbitration consists of the following:
1. Asserting a bus mastership request
2. Receiving a grant indicating that the bus is available at the end of the current bus cycle
3. Acknowledging that mastership has been assumed (3-wire bus arbitration only)
There are two ways to arbitrate the SCM68000 bus, 3-wire and 2-wire bus arbitration. Figure
3-14 and Figure 3-16 show 3-wire bus arbitration and Figure 3-15 and Figure 3-17 show 2-
wire bus arbitration. BGACKB must be negated for 2-wire bus arbitration.
The timing diagram in Figure 3-16 shows that the bus request is negated within 1.5 clocks
of the time that an acknowledge is asserted. This situation occurs when just one external
device is requesting the bus. In systems having several devices that can be bus masters,
bus request lines from these devices can be ORed at the SCM68000, and more than one
bus request signal could occur.
The bus grant signal is negated 1.5 to 3.5 clock cycles after the assertion of the bus grant
acknowledge signal. However, if bus request remains asserted (more than one device is
requesting the bus), the SCM68000 reasserts bus grant for another request a few clock
cycles after bus grant (for the previous request) is negated. In response to this additional
assertion of bus grant, external arbitration circuitry selects the next bus master before the
current bus master has completed the bus activity.
The timing diagram in Figure 3-17 shows just one external device requesting the bus. The
2-wire bus arbitration is best suited to systems with just one device, besides the CPU, capa-
ble of being bus master.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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