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參數(shù)資料
| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 138/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Exception Processing
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
4-7
Although the timing diagram in Figure 4-2 is for the 16-bit mode, the following list describes
the sequence of events executed by the processor for a vectored and autovectored interrupt
in either mode.
1. Make an internal copy of the current status register.
2. In the status register, set the S bit, clear the T bit, and replace the interrupt mask with
the level of the interrupt that was recognized. No bus activity occurs during the six
clocks required to complete steps 1 and 2.
3. Stack the lower word of the program counter on the supervisor stack.
4. Run an interrupt acknowledge bus cycle for vector number acquisition. This step takes
four clock cycles with no wait states. For an autovectored interrupt, this step takes ten
to eighteen clock cycles.
5. Justify the vector number for vector acquisition. No bus activity occurs during the four
clock periods that are required for this step.
6. Stack the status register that was saved in step 1 on the supervisor stack.
7. Stack the upper word of the program counter on the supervisor stack.
8. Read the upper word of the exception vector.
9. Read the lower word of the exception vector.
10. Fetch the first word of the first instruction of the interrupt handler routine.
11. Continue fetching instructions and executing as normal until the interrupt handling rou-
tine is complete.
4.1.5.2 AUTOVECTORED INTERRUPT ACKNOWLEDGE CYCLE. An interrupt acknowl-
edge cycle can be autovectored if AVECB is asserted instead of DTACKB in state 4 (S4).
For an autovectored interrupt, the vector number is internally generated to be $18 plus the
interrupt level. The autovector capability provides vectors for each of the six maskable inter-
rupt levels and for the nonmaskable interrupt level. The timing diagram for an autovectored
interrupt acknowledge cycle is shown in Figure 4-3.
After recognizing AVECB, the processor waits until the test clock (TESTCLK) signal is low.
Figure 4-4 shows the best-case timing of an autovectored interrupt acknowledge cycle,
while Figure 4-5 shows the worst-case timing. The cycle length is entirely dependent on the
relationship of the assertion of AVECB to the test clock.
When AVECB is recognized on the falling edge of S4 no extra wait states are inserted. The
only wait states inserted are those required to synchronize AVECB with the test clock. The
synchronization delay is an integral number of system clock cycles within the following ex-
tremes:
1. Best Case—the assertion of AVECB is recognized on the falling edge of the system
clock that occurs three clock cycles before TESTCLK rises (or three clock cycles after
TESTCLK falls).
2. Worst Case—the assertion of AVECB is recognized on the falling edge of the system
clock that occurs two clock cycles before TESTCLK rises (or four clock cycles after
TESTCLK falls).
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