MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
xi
LIST OF ILLUSTRATIONS
1-1
FlexCore Integrated Processor Typical Die Layout............................................ 1-3
1-2
Standard Cell Design Flow................................................................................. 1-6
1-3
Programming Model ........................................................................................... 1-7
1-4
Status Register................................................................................................... 1-8
1-5
Word Organization in Memory.......................................................................... 1-10
1-6
Data Organization in Memory........................................................................... 1-12
2-1
Input/Output Signals........................................................................................... 2-2
3-1
Word Read Cycle Flowchart for 16-Bit Mode ..................................................... 3-2
3-2
Byte Read Cycle Flowchart for 8-Bit Mode ........................................................ 3-3
3-3
Byte Read Cycle Flowchart for 16-Bit Mode ...................................................... 3-3
3-4
Read and Write Cycle Timing Diagram for 8-Bit Mode ...................................... 3-4
3-5
Read and Write Cycle Timing Diagram for 16-Bit Mode .................................... 3-5
3-6
Word and Byte Read Cycle Timing Diagram for 16-Bit Mode ............................ 3-6
3-7
Word Write Cycle Flowchart for 16-Bit Mode ..................................................... 3-8
3-8
Byte Write Cycle Flowchart for 8-Bit Mode......................................................... 3-9
3-9
Byte Write Cycle Flowchart for 16-Bit Mode....................................................... 3-9
3-10
Write Cycle Timing Diagram for 8-Bit Mode ..................................................... 3-10
3-11
Word and Byte Write Cycle Timing Diagram for 16-Bit Mode .......................... 3-11
3-12
Read-Modify-Write Cycle Flowchart................................................................. 3-13
3-13
Read-Modify-Write Cycle Timing Diagram ....................................................... 3-14
3-14
3-Wire Bus Arbitration Cycle Flowchart............................................................ 3-18
3-15
2-Wire Bus Arbitration Cycle Flowchart............................................................ 3-19
3-16
3-Wire Bus Arbitration Timing Diagram............................................................ 3-20
3-17
2-Wire Bus Arbitration Timing Diagram............................................................ 3-21
3-18
Bus Arbitration Unit State Diagrams................................................................. 3-23
3-19
3-Wire Bus Arbitration Timing Diagram—SCM68000 Active ........................... 3-24
3-20
3-Wire Bus Arbitration Timing Diagram—Bus Inactive..................................... 3-25
3-21
3-Wire Bus Arbitration Timing Diagram—Special Case ................................... 3-26
3-22
2-Wire Bus Arbitration Timing Diagram—SCM68000 Active ........................... 3-27
3-23
2-Wire Bus Arbitration Timing Diagram—Bus Inactive..................................... 3-28
3-24
2-Wire Bus Arbitration Timing Diagram—Special Case ................................... 3-29
3-25
Bus Error Timing Diagram................................................................................ 3-31
3-26
Retry Bus Cycle Timing Diagram ..................................................................... 3-33
3-27
Halt Operation Timing Diagram........................................................................ 3-34
3-28
External Asynchronous Signal Synchronization............................................... 3-35
3-29
Fully Asynchronous Read Cycle ...................................................................... 3-36
3-30
Fully Asynchronous Write Cycle....................................................................... 3-36
3-31
Pseudo-Asynchronous Read Cycle.................................................................. 3-37
3-32
Pseudo-Asynchronous Write Cycle.................................................................. 3-38
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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