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參數(shù)資料
| 型號： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊（SCM68000） |
| 文件頁數(shù)： | 113/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Table of Contents
viii
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
2.8
Three-State Control ...................................................................................... 2-8
2.8.1
Address Output Enable (AOEB) ................................................................. 2-8
2.8.2
Control Output Enable (COEB) .................................................................. 2-8
2.8.3
Data Output Enable (DOEB) ...................................................................... 2-8
2.9
Processor Status .......................................................................................... 2-8
2.9.1
Function Codes (FC2–FC0) ....................................................................... 2-8
2.9.2
Address Three-State Control (TSCAE) ...................................................... 2-9
2.9.3
Stop Instruction Indicator (STOP)............................................................... 2-9
2.9.4
Interrupt Pending (IPENDB) ....................................................................... 2-9
2.9.5
CPU Pipe Refill (REFILLB) ......................................................................... 2-9
2.9.6
Microsequencer Status Indication (STATUSB) .......................................... 2-9
2.10
Multiplexing Pins........................................................................................... 2-9
Section 3
Bus Operation
3.1
Data Transfer Operations ............................................................................. 3-1
3.1.1
Read Cycle ................................................................................................. 3-2
3.1.2
Write Cycle ................................................................................................. 3-8
3.1.3
Read-Modify-Write Cycle.......................................................................... 3-13
3.2
Bus Arbitration ............................................................................................ 3-17
3.2.1
Requesting the Bus .................................................................................. 3-18
3.2.2
Receiving the Bus Grant........................................................................... 3-18
3.2.3
Acknowledgment of Mastership (3-Wire Bus Arbitration Only)................. 3-19
3.3
Bus Arbitration Control................................................................................ 3-22
3.4
Bus Error and Halt Operation ..................................................................... 3-30
3.4.1
Bus Error Operation.................................................................................. 3-30
3.4.2
Retrying the Bus Cycle ............................................................................. 3-32
3.4.3
Halt Operation .......................................................................................... 3-32
3.4.4
Double Bus Fault ...................................................................................... 3-35
3.5
Asynchronous Operation ............................................................................ 3-35
3.6
Synchronous Operation .............................................................................. 3-38
3.7
The Relationship of DTACKB, BERRB, and HALTIB ................................. 3-42
Section 4
Exception Processing
4.1
Privilege Modes ............................................................................................ 4-1
4.1.1
Supervisor Mode ........................................................................................ 4-2
4.1.2
User Mode .................................................................................................. 4-2
4.1.3
Privilege Mode Changes ............................................................................ 4-2
4.1.4
Reference Classification ............................................................................. 4-3
4.1.5
CPU Space Cycle ....................................................................................... 4-3
4.1.5.1
Interrupt Acknowledge Cycle.................................................................... 4-3
4.1.5.2
Autovectored Interrupt Acknowledge Cycle ............................................. 4-7
4.2
Exception Processing Description .............................................................. 4-11
4.2.1
Exception Vectors..................................................................................... 4-11
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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