參數(shù)資料
型號： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊（SCM68000）
文件頁數(shù)： 15/145頁
文件大?。?/td> 829K
代理商： EC000UM
8-Bit Instruction Execution Times
5-2
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
5.2 MOVE INSTRUCTION EXECUTION TIMES
Table 5-2, Table 5-3, and Table 5-4 list the numbers of clock periods required for the move
instructions. The totals include instruction fetch, operand reads, and operand writes. The
total number of clock periods, the number of read cycles, and the number of write cycles are
shown in the previously described format.
Table 5-1. Effective Address Calculation Times
Addressing Mode
Byte
Word
Long
Register
Dn
An
Data Register Direct
Address Register Direct
0(0/0)
Memory
(An)
(An)+
Address Register Indirect
Address Register Indirect with Postincrement
4(1/0)
8(2/0)
16(4/0)
–(An)
(d16, An)
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
6(1/0)
12(3/0)
10(2/0)
16(4/0)
18(4/0)
24(6/0)
(d8, An, Xn)*
(xxx).W
Address Register Indirect with Index
Absolute Short
14(3/0)
12(3/0)
18(4/0)
16(4/0)
26(6/0)
24(6/0)
(xxx).L
(d16, PC)
Absolute Long
Program Counter Indirect with Displacement
20(5/0)
12(3/0)
24(6/0)
16(3/0)
32(8/0)
24(6/0)
(d8, PC, Xn)*
#<data>
Program Counter Indirect with Index
Immediate
14(3/0)
8(2/0)
18(4/0)
8(2/0)
26(6/0)
16(4/0)
*The size of the index register (Xn) does not affect execution time.
Table 5-2. Move Byte Instruction Execution Times
Source
Destination
Dn
An
(An)
(An)+
–(An)
(d16, An)
(d8, An, Xn)*
(xxx).W
(xxx).L
Dn
(An)
8(2/0)
12(3/0)
8(2/0)
12(3/0)
12(2/1)
16(3/1)
12(2/1)
16(3/1)
12(2/1)
16(3/1)
20(4/1)
24(5/1)
22(4/1)
26(5/1)
20(4/1)
24(5/1)
28(6/1)
32(7/1)
(An)+
–(An)
(d16, An)
12(3/0)
14(3/0)
20(5/0)
12(3/0)
14(3/0)
20(5/0)
16(3/1)
18(3/1)
24(5/1)
16(3/1)
18(3/1)
24(5/1)
16(3/1)
18(3/1)
24(5/1)
26(5/1)
32(7/1)
26(5/1)
28(5/1)
34(7/1)
24(5/1)
26(5/1)
32(7/1)
34(7/1)
40(9/1)
(d8, An, Xn)*
(xxx).W
(xxx).L
22(5/0)
20(5/0)
28(7/0)
22(5/0)
20(5/0)
28(7/0)
26(5/1)
24(5/1)
32(7/1)
26(5/1)
24(5/1)
32(7/1)
26(5/1)
24(5/1)
32(7/1)
34(7/1)
32(7/1)
40(9/1)
36(7/1)
34(7/1)
42(9/1)
34(7/1)
32(7/1)
40(9/1)
42(9/1)
40(9/1)
48(11/1)
(d16, PC)
(d8, PC, Xn)*
#<data>
20(5/0)
22(5/0)
16(4/0)
20(5/0)
22(5/0)
16(4/0)
24(5/1)
26(5/1)
20(4/1)
24(5/1)
26(5/1)
20(4/1)
24(5/1)
26(5/1)
20(4/1)
32(7/1)
34(7/1)
28(6/1)
34(7/1)
36(7/1)
30(6/1)
32(7/1)
34(7/1)
28(6/1)
40(9/1)
42(9/1)
36(8/1)
*The size of the index register (Xn) does not affect execution time.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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