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| 型號(hào)： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶(hù)手冊(cè)（SCM68000） |
| 文件頁(yè)數(shù)： | 70/145頁(yè) |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
2-1
SECTION 2
SIGNAL DESCRIPTION
This section contains descriptions of the SCM68000 (EC000 core)1 input and output signals.
The input and output signals are shown in Figure 2-1. Table 2-1 lists the pins, signal names,
type, and whether they are three-stateable. The following paragraphs provide brief descrip-
tions of the signals and references (where applicable) to other paragraphs that contain more
information about the signals.
NOTE
The terms
assertion and negation are used extensively in this
manual to avoid confusion when describing a mixture of "active-
low" and "active-high" signals. The term
assert or assertion is
used to indicate that a signal is active or true, independently of
whether that level is represented by a high or low voltage. The
term
negate or negation is used to indicate that a signal is inac-
tive or false.
2.1 ADDRESS BUS (A31–A0)
This 32-bit, unidirectional, three-state bus is capable of addressing 4 Gbytes of address
space. This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3
provide the level number of the interrupt being acknowledged, and address lines A31–A4
and A0 are driven to a logic high.
2.2 DATA BUS (D15–D0)
This 16-bit, bidirectional, three-state bus is the general-purpose data-path. The data bus
transfers and accepts data in either word or byte length if the SCM68000 is operating in the
16-bit mode. If the SCM68000 is operating in the 8-bit mode, it drives the entire bus during
writes, but only the lower eight bits (D7–D0) contain valid data. In the 8-bit mode, the
SCM68000 ignores the data on data lines D15–D8 during read cycles. During an interrupt
acknowledge cycle, the external device supplies the vector number on data lines D7–D0.
2.3 CLOCK (CLKI, CLKO)
The CLKI input is internally buffered for development of the internal clocks needed by the
SCM68000. This clock signal is a constant-frequency square wave that requires no stretch-
ing or shaping. The clock signal must conform to minimum and maximum pulse-width times
1. The SCM68000 is the name of the Verilog model for the EC000 core. The remainder of this section will
refer to the EC000 core as only the SCM68000.
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相關(guān)代理商/技術(shù)參數(shù) |
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| EC0010-000 | 制造商:TE Connectivity 功能描述:EC0010-000 |
| EC001031 | 制造商:PHOENIX 制造商全稱(chēng):PHOENIX CONTACT 功能描述:Header, Nominal current: 12 A, Rated voltage (III/2): 320 V, Assembly: Soldering |
| EC001121 | 制造商:PHOENIX 制造商全稱(chēng):PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 4, Pitch: 5mm, Connection method: Screw connection, Color: Black, Contact surface: Tin |
| EC001283 | 制造商:PHOENIX 制造商全稱(chēng):PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 7, Pitch: 5.08 mm, Connection method: Solder/Slip-on connection, Color: green, Contact surface: Tin, Assembly: Direct mounting |
| EC0013-000 | 制造商:TE Connectivity 功能描述:EC0013-000 |
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