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參數(shù)資料
| 型號(hào)： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊(cè)（SCM68000） |
| 文件頁(yè)數(shù)： | 56/145頁(yè) |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Overview
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
1-5
1.2 DEVELOPMENT CYCLE
There are several steps that must be followed in order to create a FlexCore integrated mi-
croprocessor with an SCM68000. Figure 1-2 illustrates the standard cell design flow and the
tools required to complete each step. These steps include:
Convert Design to Standard Cells Design—Begin by implementing the required system
functions with an SCM68000, peripherals, memory blocks, and cells from the Motorola
standard cell library.
Capture Design on Workstation—Use the engineering workstation to capture the logic
schematic of cells and their interconnections.
Logic Synthesis—The structural level description of the design is mapped to a more ef-
ficient structural description, which is accomplished by converting the Boolean equa-
tions for the design to a two-level sum of products representation and minimized.
Generate Test Patterns—The stimulus and test patterns for the design are generated
for the functional simulation.
Functional Simulation—Ensure that the logic of the schematic is functionally sound by
using Verilog, the encrypted C models and synthesis models provided by Motorola. No
timing information is yet associated with the simulations, and all propagation delays are
preset to 1 ns.
Calculate Node Delays— Motorola software (mdaDecal) calculates the estimated prop-
agation delays of each node in the circuit. The design software estimates delays based
on the fanout, drive characteristics, and estimated interconnect capacitances of the
netlist and reveals potential timing problems.
Path Delay Analysis—With path delay information from the Veritime software, the de-
lays between the clocked elements of the circuit can be determined, and the critical
paths that limit the clock rate can be identified. Checking for setup, hold, and pulse-
width violations can also be accomplished.
Perform Real-Time Simulation—The real-time simulation is run to verify full functionality
using the estimated propagation delays calculated by the design tools.
Extract Test Vectors—The simulator records the input/output patterns generated during
the real-time simulation. The test vectors that Motorola will use to test the prototypes
are derived from these patterns.
Automatic Place & Route—The circuit’s physical layout is created from the netlist using
automatic place and route software.
Interconnect Analysis—After the cells are placed and routed, the interconnect capaci-
tances are extracted. These capacitances replace those estimated earlier during the
calculation of the node delays.
Re-Simulate—The circuit is re-simulated with Verilog to ensure no problems have aris-
en due to a change in load conditions. If changes have occurred or the simulation is dif-
ferent in any way, the test vectors must also be extracted again.
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For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| EC0010-000 | 制造商:TE Connectivity 功能描述:EC0010-000 |
| EC001031 | 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Header, Nominal current: 12 A, Rated voltage (III/2): 320 V, Assembly: Soldering |
| EC001121 | 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 4, Pitch: 5mm, Connection method: Screw connection, Color: Black, Contact surface: Tin |
| EC001283 | 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 7, Pitch: 5.08 mm, Connection method: Solder/Slip-on connection, Color: green, Contact surface: Tin, Assembly: Direct mounting |
| EC0013-000 | 制造商:TE Connectivity 功能描述:EC0013-000 |
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