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參數(shù)資料
| 型號(hào)： | EC000UM |
| 英文描述： | EC000 Core User＇s Manual (SCM68000) |
| 中文描述： | EC000核心用戶手冊(cè)（SCM68000） |
| 文件頁數(shù)： | 122/145頁 |
| 文件大?。?/td> | 829K |
| 代理商： | EC000UM |
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Bus Operation
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
3-37
A device can use a clock at the same frequency as the system clock, but without a defined
phase relationship to the system clock. This mode of operation is pseudo-asynchronous; it
increases performance by observing timing parameters related to the system clock fre-
quency without being completely synchronous with that clock. A common example of a
pseudo-asynchronous device is a memory array designed to operate with the SCM68000 at
a certain frequency but is not driven by the SCM68000 clock.
The designer of a fully asynchronous system can make no assumptions about address
setup time, which could be used to improve performance. However, with the system clock
frequency known, the slave device can be designed to decode the address bus before rec-
ognizing an address strobe. Parameter #11 (refer to Section 7 Electrical Characteristics
for all parameters listed in this section) specifies the minimum time before address strobe
during which the address is valid.
In a pseudo-asynchronous system, timing specifications allow DTACKB to be asserted for
a read cycle (see Figure 3-31) before the data from a slave device is valid. The length of
time that DTACKB may precede data is specified as parameter #31 in Figure 3-31. This
parameter must be met to ensure the validity of the data latched into the SCM68000. No
maximum time is specified from the assertion of ASB to the assertion of DTACKB. During
this unlimited time, the SCM68000 inserts wait cycles in one-clock-period increments until
DTACKB is recognized. Figure 3-31 shows the important timing parameters for a pseudo-
asynchronous read cycle.
During a write cycle (see Figure 3-32), after the SCM68000 asserts ASB but before driving
the data bus, the SCM68000 drives RWB to a logic low. Parameter #55 specifies the mini-
Figure 3-31. Pseudo-Asynchronous Read Cycle
A31–A0
ASB
RWB
DATA
DTACKB
17
31
29
15
13
UDSB and/or LDSB
and DSB
11
28
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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